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W11 CPU core and support modules
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pdp11_hio70_artys7.vhd
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1-- $Id: pdp11_hio70_artys7.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: pdp11_hio70_artys7 - syn
7-- Description: pdp11: hio led and rgb for sys70 for artys7
8--
9-- Dependencies: -
10-- Test bench: -
11-- Target Devices: generic
12-- Tool versions: viv 2017.2-2018.2; ghdl 0.34
13--
14-- Revision History:
15-- Date Rev Version Comment
16-- 2018-10-07 1054 1.1 use DM_STAT_EXP instead of DM_STAT_DP
17-- 2018-08-05 1038 1.0 Initial version (cloned from pdp11_hio70_artya7)
18------------------------------------------------------------------------------
19--
20-- collects the output for LED and RGB leds
21-- MODE = 00xy
22-- LED IO activity
23-- (3) not SER_MONI.txok (shows tx back pressure)
24-- (2) SER_MONI.txact (shows tx activity)
25-- (1) not SER_MONI.rxok (shows rx back pressure)
26-- (0) SER_MONI.rxact (shows rx activity)
27-- RGB_G CPU busy (active cpugo=1, enabled with y=1)
28-- (1) kernel mode, non-wait
29-- (0) user or supervisor mode
30-- RGB_R CPU rust (active cpugo=0, enabled with y=1)
31-- (1:0) cpurust code
32-- RGB_B MEM/cmd busy (enabled with x=1)
33-- (1) cmdbusy (all rlink access, mostly rdma)
34-- (0) not cpugo
35--
36-- MODE = 0100 (DR emulation)
37-- LED DR(15:12)
38-- RGB_B DR( 9:08)
39-- RGB_G DR( 5:04)
40-- RGB_R DR( 1:00)
41--
42-- MODE = 1xyy (show lsb or msb of 16 bit register)
43-- LED show bit 7:4, RGB_G bit 1:0; x=0 shows lsb and x=1 shows msb
44-- yy = 00: abclkdiv & abclkdiv_f
45-- 01: PC
46-- 10: DISPREG
47-- 11: DR emulation
48--
49
50library ieee;
51use ieee.std_logic_1164.all;
52use ieee.numeric_std.all;
53
54use work.slvtypes.all;
55use work.pdp11.all;
56
57-- ----------------------------------------------------------------------------
58
59entity pdp11_hio70_artys7 is -- hio led+rgb for sys70 for artys7
60 port (
61 CLK : in slbit; -- clock
62 MODE : in slv4; -- mode select
63 MEM_ACT_R : in slbit; -- memory active read
64 MEM_ACT_W : in slbit; -- memory active write
65 CP_STAT : in cp_stat_type; -- console port status
66 DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
67 DISPREG : in slv16; -- display register
68 IOLEDS : in slv4; -- serport ioleds
69 ABCLKDIV : in slv16; -- serport clock divider
70 LED : out slv4; -- hio leds
71 RGB_R : out slv2; -- hio rgb leds - red
72 RGB_G : out slv2; -- hio rgb leds - green
73 RGB_B : out slv2 -- hio rgb leds - blue
74 );
76
77architecture syn of pdp11_hio70_artys7 is
78
79 signal R_LED : slv4 := (others=>'0');
80 signal R_RGB_R : slv2 := (others=>'0');
81 signal R_RGB_G : slv2 := (others=>'0');
82 signal R_RGB_B : slv2 := (others=>'0');
83
84begin
85
86 proc_regs : process (CLK)
87 variable idat16 : slv16 := (others=>'0');
88 variable idat8 : slv8 := (others=>'0');
89 variable iled : slv4 := (others=>'0');
90 variable irgb_r : slv2 := (others=>'0');
91 variable irgb_g : slv2 := (others=>'0');
92 variable irgb_b : slv2 := (others=>'0');
93 begin
94 if rising_edge(CLK) then
95
96 idat16 := (others=>'0');
97 case MODE(1 downto 0) is
98 when "00" => idat16 := ABCLKDIV;
99 when "01" => idat16 := DM_STAT_EXP.dp_pc;
100 when "10" => idat16 := DISPREG;
101 when "11" => idat16 := DM_STAT_EXP.dp_dsrc;
102 when others => null;
103 end case;
104
105 if MODE(2) = '0' then
106 idat8 := idat16( 7 downto 0);
107 else
108 idat8 := idat16(15 downto 8);
109 end if;
110
111 iled := (others=>'0');
112 irgb_r := (others=>'0');
113 irgb_g := (others=>'0');
114 irgb_b := (others=>'0');
115
116 if MODE(3) = '0' then
117 if MODE(2) = '0' then -- LED shows IO; RGB shows CPU/MEM
118 iled := IOLEDS;
119
120 if MODE(0) = '1' then
121 if CP_STAT.cpugo = '1' then
122 case DM_STAT_EXP.dp_psw.cmode is
123 when c_psw_kmode =>
124 if CP_STAT.cpuwait = '0' then
125 irgb_g(1) := '1';
126 end if;
127 when c_psw_smode =>
128 irgb_g(0) := '1';
129 when c_psw_umode =>
130 irgb_g(0) := '1';
131 when others => null;
132 end case;
133 else
134 irgb_r(1 downto 0) := CP_STAT.cpurust(1 downto 0);
135 end if;
136 end if; -- MODE(0) = '1'
137
138 if MODE(1) = '1' then
139 irgb_b(1) := CP_STAT.cmdbusy;
140 irgb_b(0) := not CP_STAT.cpugo;
141 end if;
142
143 else -- LED+RGB show DR emulation
144 iled := DM_STAT_EXP.dp_dsrc(15 downto 12);
145 irgb_b := DM_STAT_EXP.dp_dsrc( 9 downto 8);
146 irgb_g := DM_STAT_EXP.dp_dsrc( 5 downto 4);
147 irgb_r := DM_STAT_EXP.dp_dsrc( 1 downto 0);
148 end if; -- MODE(2) = '0'
149
150 else -- LED+RGB show one of four regs
151 iled := idat8(7 downto 4);
152 irgb_g := idat8(1 downto 0);
153 end if; -- MODE(3) = '0'
154
155 R_LED <= iled;
156 R_RGB_R <= irgb_r;
157 R_RGB_G <= irgb_g;
158 R_RGB_B <= irgb_b;
159 end if;
160
161 end process proc_regs;
162
163 LED <= R_LED;
164 RGB_R <= R_RGB_R;
165 RGB_G <= R_RGB_G;
166 RGB_B <= R_RGB_B;
167
168end syn;
slv2 :=( others => '0') R_RGB_G
slv2 :=( others => '0') R_RGB_B
slv2 :=( others => '0') R_RGB_R
slv4 :=( others => '0') R_LED
in CP_STAT cp_stat_type
in DM_STAT_EXP dm_stat_exp_type
Definition: pdp11.vhd:123
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34