51use ieee.std_logic_1164.
all;
52use ieee.numeric_std.
all;
86 proc_regs :
process (
CLK)
87 variable idat16 : slv16 := (others=>'0');
88 variable idat8 : slv8 := (others=>'0');
89 variable iled : slv4 := (others=>'0');
90 variable irgb_r : slv2 := (others=>'0');
91 variable irgb_g : slv2 := (others=>'0');
92 variable irgb_b : slv2 := (others=>'0');
94 if rising_edge(CLK) then
96 idat16 := (others=>'0');
97 case MODE(1 downto 0) is
100 when "10" => idat16 := DISPREG;
105 if MODE(2) = '0' then
106 idat8 := idat16( 7 downto 0);
108 idat8 := idat16(15 downto 8);
111 iled := (others=>'0');
112 irgb_r := (others=>'0');
113 irgb_g := (others=>'0');
114 irgb_b := (others=>'0');
116 if MODE(3) = '0' then
117 if MODE(2) = '0' then
120 if MODE(0) = '1' then
134 irgb_r(1 downto 0) := CP_STAT.cpurust(1 downto 0);
138 if MODE(1) = '1' then
140 irgb_b(0) := not CP_STAT.cpugo;
151 iled := idat8(7 downto 4);
152 irgb_g := idat8(1 downto 0);
161 end process proc_regs;
slv2 :=( others => '0') R_RGB_G
slv2 :=( others => '0') R_RGB_B
slv2 :=( others => '0') R_RGB_R
slv4 :=( others => '0') R_LED
in DM_STAT_EXP dm_stat_exp_type
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 7 downto 0) slv8
std_logic_vector( 1 downto 0) slv2