syn Architecture Reference

Architecture >> syn

Processes
proc_clka	( CLKA )
proc_clkb	( CLKB )

Constants
memsize	positive := 2 ** AWIDTH
datzero	slv ( DWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Types
ram_type	( 0 to memsize - 1 ) slv ( DWIDTH - 1 downto 0 )

Signals
R_DOA	slv ( DWIDTH - 1 downto 0 ) := datzero
R_DOB	slv ( DWIDTH - 1 downto 0 ) := datzero

Attributes
ram_style	string
ram_style	variable is " block "

Shared Variables
sv_ram	shared ram_type := := ( others = > datzero )

Instantiations
umem	ram_2swsr_xfirst_gen_unisim <Entity ram_2swsr_xfirst_gen_unisim>

Detailed Description

Definition at line 53 of file ram_2swsr_wfirst_gen.vhd.

Member Function/Procedure/Process Documentation

proc_clka()

proc_clka (   CLKA   )

Process

Definition at line 66 of file ram_2swsr_wfirst_gen.vhd.

proc_clkb()

proc_clkb (   CLKB   )

Process

Definition at line 78 of file ram_2swsr_wfirst_gen.vhd.

Member Data Documentation

memsize

memsize positive := 2 ** AWIDTH

Constant

Definition at line 54 of file ram_2swsr_wfirst_gen.vhd.

datzero

datzero slv ( DWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Constant

Definition at line 55 of file ram_2swsr_wfirst_gen.vhd.

ram_type

ram_type ( 0 to memsize - 1 ) slv ( DWIDTH - 1 downto 0 )

Type

Definition at line 56 of file ram_2swsr_wfirst_gen.vhd.

sv_ram

sv_ram shared ram_type := := ( others = > datzero )

Shared Variable

Definition at line 57 of file ram_2swsr_wfirst_gen.vhd.

ram_style [1/2]

ram_style string

Attribute

Definition at line 59 of file ram_2swsr_wfirst_gen.vhd.

ram_style [2/2]

ram_style variable is " block "

Attribute

Definition at line 60 of file ram_2swsr_wfirst_gen.vhd.

R_DOA

R_DOA slv ( DWIDTH - 1 downto 0 ) := datzero

Signal

Definition at line 62 of file ram_2swsr_wfirst_gen.vhd.

R_DOB

R_DOB slv ( DWIDTH - 1 downto 0 ) := datzero

Signal

Definition at line 63 of file ram_2swsr_wfirst_gen.vhd.

umem

umem ram_2swsr_xfirst_gen_unisim

Instantiation

Definition at line 72 of file ram_2swsr_wfirst_gen_unisim.vhd.

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The documentation for this design unit was generated from the following file:

• vlib/memlib/ram_2swsr_wfirst_gen.vhd