w11 - vhd 0.794
W11 CPU core and support modules
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rgbdrv_analog Entity Reference
Inheritance diagram for rgbdrv_analog:
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Collaboration diagram for rgbdrv_analog:
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Entities

syn  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
numeric_std 
slvtypes  Package <slvtypes>
xlib  Package <xlib>

Generics

DWIDTH  positive := 8
ACTLOW  slbit := ' 0 '

Ports

CLK   in   slbit
RESET   in   slbit := ' 0 '
RGBCNTL   in   slv3
DIMCNTL   in   slv ( DWIDTH - 1 downto 0 )
DIMR   in   slv ( DWIDTH - 1 downto 0 )
DIMG   in   slv ( DWIDTH - 1 downto 0 )
DIMB   in   slv ( DWIDTH - 1 downto 0 )
O_RGBLED   out   slv3

Detailed Description

Definition at line 27 of file rgbdrv_analog.vhd.

Member Data Documentation

◆ DWIDTH

DWIDTH positive := 8
Generic

Definition at line 29 of file rgbdrv_analog.vhd.

◆ ACTLOW

ACTLOW slbit := ' 0 '
Generic

Definition at line 30 of file rgbdrv_analog.vhd.

◆ CLK

CLK in slbit
Port

Definition at line 32 of file rgbdrv_analog.vhd.

◆ RESET

RESET in slbit := ' 0 '
Port

Definition at line 33 of file rgbdrv_analog.vhd.

◆ RGBCNTL

RGBCNTL in slv3
Port

Definition at line 34 of file rgbdrv_analog.vhd.

◆ DIMCNTL

DIMCNTL in slv ( DWIDTH - 1 downto 0 )
Port

Definition at line 35 of file rgbdrv_analog.vhd.

◆ DIMR

DIMR in slv ( DWIDTH - 1 downto 0 )
Port

Definition at line 36 of file rgbdrv_analog.vhd.

◆ DIMG

DIMG in slv ( DWIDTH - 1 downto 0 )
Port

Definition at line 37 of file rgbdrv_analog.vhd.

◆ DIMB

DIMB in slv ( DWIDTH - 1 downto 0 )
Port

Definition at line 38 of file rgbdrv_analog.vhd.

◆ O_RGBLED

O_RGBLED out slv3
Port

Definition at line 40 of file rgbdrv_analog.vhd.

◆ ieee

ieee
Library

Definition at line 20 of file rgbdrv_analog.vhd.

◆ std_logic_1164

std_logic_1164
use clause

Definition at line 21 of file rgbdrv_analog.vhd.

◆ numeric_std

numeric_std
use clause

Definition at line 22 of file rgbdrv_analog.vhd.

◆ slvtypes

slvtypes
use clause

Definition at line 24 of file rgbdrv_analog.vhd.

◆ xlib

xlib
use clause

Definition at line 25 of file rgbdrv_analog.vhd.


The documentation for this design unit was generated from the following file: