w11 - vhd 0.794
W11 CPU core and support modules
Loading...
Searching...
No Matches
rgbdrv_analog.vhd
Go to the documentation of this file.
1-- $Id: rgbdrv_analog.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2016-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: rgbdrv_analog - syn
7-- Description: rgbled driver: analog channel
8--
9-- Dependencies: -
10-- Test bench: -
11-- Target Devices: generic
12-- Tool versions: viv 2015.4-2016.4; ghdl 0.31-0.34
13--
14-- Revision History:
15-- Date Rev Version Comment
16-- 2017-06-05 907 1.1 add ACTLOW generic to invert output polarity
17-- 2016-02-20 734 1.0 Initial version
18------------------------------------------------------------------------------
19
20library ieee;
21use ieee.std_logic_1164.all;
22use ieee.numeric_std.all;
23
24use work.slvtypes.all;
25use work.xlib.all;
26
27entity rgbdrv_analog is -- rgbled driver: analog channel
28 generic (
29 DWIDTH : positive := 8; -- dimmer width
30 ACTLOW : slbit := '0'); -- invert output polarity
31 port (
32 CLK : in slbit; -- clock
33 RESET : in slbit := '0'; -- reset
34 RGBCNTL : in slv3; -- rgb control
35 DIMCNTL : in slv(DWIDTH-1 downto 0);-- dim control
36 DIMR : in slv(DWIDTH-1 downto 0); -- dim red
37 DIMG : in slv(DWIDTH-1 downto 0); -- dim green
38 DIMB : in slv(DWIDTH-1 downto 0); -- dim blue
39 O_RGBLED : out slv3 -- pad-o: rgb led
40 );
42
43architecture syn of rgbdrv_analog is
44
45 signal R_RGB : slv3 := (others=>'0'); -- state registers
46 signal N_RGB : slv3 := (others=>'0'); -- next value state regs
47
48begin
49
50 IOB_RGB : iob_reg_o_gen
51 generic map (DWIDTH => 3)
52 port map (CLK => CLK, CE => '1', DO => R_RGB, PAD => O_RGBLED);
53
54 proc_regs: process (CLK)
55 begin
56
57 if rising_edge(CLK) then
58 if RESET = '1' then
59 R_RGB <= (others=>'0');
60 else
61 R_RGB <= N_RGB;
62 end if;
63 end if;
64
65 end process proc_regs;
66
67
68 proc_next: process (R_RGB, RGBCNTL, DIMCNTL, DIMR, DIMG, DIMB)
69 variable irgb : slv3 := (others=>'0');
70 begin
71
72 irgb := (others=>'0');
73
74 if unsigned(DIMCNTL) < unsigned(DIMR) then
75 irgb(0) := RGBCNTL(0);
76 end if;
77
78 if unsigned(DIMCNTL) < unsigned(DIMG) then
79 irgb(1) := RGBCNTL(1);
80 end if;
81
82 if unsigned(DIMCNTL) < unsigned(DIMB) then
83 irgb(2) := RGBCNTL(2);
84 end if;
85
86 N_RGB(0) <= ACTLOW xor irgb(0);
87 N_RGB(1) <= ACTLOW xor irgb(1);
88 N_RGB(2) <= ACTLOW xor irgb(2);
89
90 end process proc_next;
91
92
93end syn;
in CE slbit := '1'
out PAD slv( DWIDTH- 1 downto 0)
in CLK slbit
in DO slv( DWIDTH- 1 downto 0)
DWIDTH positive := 16
slv3 :=( others => '0') R_RGB
slv3 :=( others => '0') N_RGB
in RGBCNTL slv3
DWIDTH positive := 8
out O_RGBLED slv3
in DIMB slv( DWIDTH- 1 downto 0)
in DIMCNTL slv( DWIDTH- 1 downto 0)
in DIMG slv( DWIDTH- 1 downto 0)
ACTLOW slbit := '0'
in CLK slbit
in DIMR slv( DWIDTH- 1 downto 0)
in RESET slbit := '0'
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector slv
Definition: slvtypes.vhd:31
Definition: xlib.vhd:35