21use ieee.std_logic_1164.
all;
22use ieee.numeric_std.
all;
54 proc_regs:
process (
CLK)
57 if rising_edge(CLK) then
59 R_RGB <= (others=>'0');
65 end process proc_regs;
69 variable irgb : slv3 := (others=>'0');
72 irgb := (others=>'0');
90 end process proc_next;
out PAD slv( DWIDTH- 1 downto 0)
in DO slv( DWIDTH- 1 downto 0)
slv3 :=( others => '0') R_RGB
slv3 :=( others => '0') N_RGB
in DIMB slv( DWIDTH- 1 downto 0)
in DIMCNTL slv( DWIDTH- 1 downto 0)
in DIMG slv( DWIDTH- 1 downto 0)
in DIMR slv( DWIDTH- 1 downto 0)
std_logic_vector( 2 downto 0) slv3