syn Architecture Reference

Architecture >> syn

Signals
CLK	slbit := ' 0 '
SWI	slv8 := ( others = > ' 0 ' )
BTN	slv5 := ( others = > ' 0 ' )
LED	slv8 := ( others = > ' 0 ' )
DSP_DAT	slv16 := ( others = > ' 0 ' )
DSP_DP	slv4 := ( others = > ' 0 ' )
RESET	slbit := ' 0 '
CE_MSEC	slbit := ' 0 '

Instantiations
clkdiv	clkdivce <Entity clkdivce>
hio	sn_humanio <Entity sn_humanio>
hiotest	tst_snhumanio <Entity tst_snhumanio>

Detailed Description

Definition at line 56 of file sys_tst_snhumanio_b3.vhd.

Member Data Documentation

CLK

CLK slbit := ' 0 '

Signal

Definition at line 58 of file sys_tst_snhumanio_b3.vhd.

SWI

SWI slv8 := ( others = > ' 0 ' )

Signal

Definition at line 60 of file sys_tst_snhumanio_b3.vhd.

BTN

BTN slv5 := ( others = > ' 0 ' )

Signal

Definition at line 61 of file sys_tst_snhumanio_b3.vhd.

LED

LED slv8 := ( others = > ' 0 ' )

Signal

Definition at line 62 of file sys_tst_snhumanio_b3.vhd.

DSP_DAT

DSP_DAT slv16 := ( others = > ' 0 ' )

Signal

Definition at line 63 of file sys_tst_snhumanio_b3.vhd.

DSP_DP

DSP_DP slv4 := ( others = > ' 0 ' )

Signal

Definition at line 64 of file sys_tst_snhumanio_b3.vhd.

RESET

RESET slbit := ' 0 '

Signal

Definition at line 66 of file sys_tst_snhumanio_b3.vhd.

CE_MSEC

CE_MSEC slbit := ' 0 '

Signal

Definition at line 67 of file sys_tst_snhumanio_b3.vhd.

clkdiv

clkdiv clkdivce

Instantiation

Definition at line 84 of file sys_tst_snhumanio_b3.vhd.

hio

hio sn_humanio

Instantiation

Definition at line 104 of file sys_tst_snhumanio_b3.vhd.

hiotest

hiotest tst_snhumanio

Instantiation

Definition at line 118 of file sys_tst_snhumanio_b3.vhd.

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The documentation for this design unit was generated from the following file:

• sys_gen/tst_snhumanio/basys3/sys_tst_snhumanio_b3.vhd