w11 - vhd 0.794
W11 CPU core and support modules
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Constants | Instantiations | Processes | Signals
sim Architecture Reference
Architecture >> sim

Processes

proc_simbus  ( SB_VAL )

Constants

sbaddr_swi  slv8 := slv ( to_unsigned ( 16 , 8 ) )
sbaddr_btn  slv8 := slv ( to_unsigned ( 17 , 8 ) )
pcb_delay  Delay_length := 1 ns

Signals

MM_MEM_CE_N  slbit := ' 1 '
MM_MEM_BE_N  slv2 := ( others = > ' 1 ' )
MM_MEM_WE_N  slbit := ' 1 '
MM_MEM_OE_N  slbit := ' 1 '
MM_MEM_ADV_N  slbit := ' 1 '
MM_MEM_CLK  slbit := ' 0 '
MM_MEM_CRE  slbit := ' 0 '
MM_MEM_WAIT  slbit := ' 0 '
MM_MEM_ADDR  slv23 := ( others = > ' Z ' )
MM_MEM_DATA  slv16 := ( others = > ' 0 ' )
R_SWI  slv8 := ( others = > ' 0 ' )
R_BTN  slv5 := ( others = > ' 0 ' )

Instantiations

busdly  simbididly <Entity simbididly>
mem  mt45w8mw16b <Entity mt45w8mw16b>

Detailed Description

Definition at line 49 of file tb_nexys3_core.vhd.

Member Function/Procedure/Process Documentation

◆ proc_simbus()

proc_simbus (   SB_VAL)

Definition at line 104 of file tb_nexys3_core.vhd.

Member Data Documentation

◆ MM_MEM_CE_N

MM_MEM_CE_N slbit := ' 1 '
Signal

Definition at line 51 of file tb_nexys3_core.vhd.

◆ MM_MEM_BE_N

MM_MEM_BE_N slv2 := ( others = > ' 1 ' )
Signal

Definition at line 52 of file tb_nexys3_core.vhd.

◆ MM_MEM_WE_N

MM_MEM_WE_N slbit := ' 1 '
Signal

Definition at line 53 of file tb_nexys3_core.vhd.

◆ MM_MEM_OE_N

MM_MEM_OE_N slbit := ' 1 '
Signal

Definition at line 54 of file tb_nexys3_core.vhd.

◆ MM_MEM_ADV_N

MM_MEM_ADV_N slbit := ' 1 '
Signal

Definition at line 55 of file tb_nexys3_core.vhd.

◆ MM_MEM_CLK

MM_MEM_CLK slbit := ' 0 '
Signal

Definition at line 56 of file tb_nexys3_core.vhd.

◆ MM_MEM_CRE

MM_MEM_CRE slbit := ' 0 '
Signal

Definition at line 57 of file tb_nexys3_core.vhd.

◆ MM_MEM_WAIT

MM_MEM_WAIT slbit := ' 0 '
Signal

Definition at line 58 of file tb_nexys3_core.vhd.

◆ MM_MEM_ADDR

MM_MEM_ADDR slv23 := ( others = > ' Z ' )
Signal

Definition at line 59 of file tb_nexys3_core.vhd.

◆ MM_MEM_DATA

MM_MEM_DATA slv16 := ( others = > ' 0 ' )
Signal

Definition at line 60 of file tb_nexys3_core.vhd.

◆ R_SWI

R_SWI slv8 := ( others = > ' 0 ' )
Signal

Definition at line 62 of file tb_nexys3_core.vhd.

◆ R_BTN

R_BTN slv5 := ( others = > ' 0 ' )
Signal

Definition at line 63 of file tb_nexys3_core.vhd.

◆ sbaddr_swi

sbaddr_swi slv8 := slv ( to_unsigned ( 16 , 8 ) )
Constant

Definition at line 65 of file tb_nexys3_core.vhd.

◆ sbaddr_btn

sbaddr_btn slv8 := slv ( to_unsigned ( 17 , 8 ) )
Constant

Definition at line 66 of file tb_nexys3_core.vhd.

◆ pcb_delay

pcb_delay Delay_length := 1 ns
Constant

Definition at line 67 of file tb_nexys3_core.vhd.

◆ busdly

busdly simbididly
Instantiation

Definition at line 87 of file tb_nexys3_core.vhd.

◆ mem

mem mt45w8mw16b
Instantiation

Definition at line 102 of file tb_nexys3_core.vhd.

The documentation for this design unit was generated from the following file: