w11 - vhd 0.794
W11 CPU core and support modules
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ib_intmap.vhd
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1-- $Id: ib_intmap.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2006-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: ib_intmap - syn
7-- Description: pdp11: external interrupt mapper (15 line)
8--
9-- Dependencies: -
10-- Test bench: tb/tb_pdp11_core (implicit)
11-- Target Devices: generic
12-- Tool versions: ise 8.2-14.7; viv 2014.4-2017.2; ghdl 0.18-0.35
13--
14-- Synthesized:
15-- Date Rev viv Target flop lutl lutm bram slic MHz
16-- 2016-05-26 641 2016.4 xc7a100t-1 0 30 0 0 - -
17-- 2015-02-22 641 i 14.7 xc6slx16-2 0 20 0 0 9 -
18--
19-- Revision History:
20-- Date Rev Version Comment
21-- 2019-04-23 1136 1.2 BUGFIX: ensure ACK send to correct device
22-- 2011-11-18 427 1.2.2 now numeric_std clean
23-- 2008-08-22 161 1.2.1 renamed pdp11_ -> ib_; use iblib
24-- 2008-01-20 112 1.2 add INTMAP generic to externalize config
25-- 2008-01-06 111 1.1 add EI_ACK output lines, remove EI_LINE
26-- 2007-10-12 88 1.0.2 avoid ieee.std_logic_unsigned, use cast to unsigned
27-- 2007-06-14 56 1.0.1 Use slvtypes.all
28-- 2007-05-12 26 1.0 Initial version
29------------------------------------------------------------------------------
30
31library ieee;
32use ieee.std_logic_1164.all;
33use ieee.numeric_std.all;
34
35use work.slvtypes.all;
36use work.iblib.all;
37
38-- ----------------------------------------------------------------------------
39
40entity ib_intmap is -- external interrupt mapper
41 generic (
42 INTMAP : intmap_array_type := intmap_array_init);
43 port (
44 CLK : in slbit; -- clock
45 EI_REQ : in slv16_1; -- interrupt request lines
46 EI_ACKM : in slbit; -- interrupt acknowledge (from master)
47 EI_ACK : out slv16_1; -- interrupt acknowledge (to requestor)
48 EI_PRI : out slv3; -- interrupt priority
49 EI_VECT : out slv9_2 -- interrupt vector
50 );
51end ib_intmap;
52
53architecture syn of ib_intmap is
54
55 signal EI_LINE : slv4 := (others=>'0'); -- external interrupt line
56 signal R_LINE : slv4 := (others=>'0'); -- line on last cycle
57
58 type intp_type is array (15 downto 0) of slv3;
59 type intv_type is array (15 downto 0) of slv9;
60
61 constant conf_intp : intp_type :=
62 (slv(to_unsigned(INTMAP(15).pri,3)), -- line 15
63 slv(to_unsigned(INTMAP(14).pri,3)), -- line 14
64 slv(to_unsigned(INTMAP(13).pri,3)), -- line 13
65 slv(to_unsigned(INTMAP(12).pri,3)), -- line 12
66 slv(to_unsigned(INTMAP(11).pri,3)), -- line 11
67 slv(to_unsigned(INTMAP(10).pri,3)), -- line 10
68 slv(to_unsigned(INTMAP( 9).pri,3)), -- line 9
69 slv(to_unsigned(INTMAP( 8).pri,3)), -- line 8
70 slv(to_unsigned(INTMAP( 7).pri,3)), -- line 7
71 slv(to_unsigned(INTMAP( 6).pri,3)), -- line 6
72 slv(to_unsigned(INTMAP( 5).pri,3)), -- line 5
73 slv(to_unsigned(INTMAP( 4).pri,3)), -- line 4
74 slv(to_unsigned(INTMAP( 3).pri,3)), -- line 3
75 slv(to_unsigned(INTMAP( 2).pri,3)), -- line 2
76 slv(to_unsigned(INTMAP( 1).pri,3)), -- line 1
77 slv(to_unsigned( 0,3)) -- line 0 (always 0 !!)
78 );
79
80 constant conf_intv : intv_type :=
81 (slv(to_unsigned(INTMAP(15).vec,9)), -- line 15
82 slv(to_unsigned(INTMAP(14).vec,9)), -- line 14
83 slv(to_unsigned(INTMAP(13).vec,9)), -- line 13
84 slv(to_unsigned(INTMAP(12).vec,9)), -- line 12
85 slv(to_unsigned(INTMAP(11).vec,9)), -- line 11
86 slv(to_unsigned(INTMAP(10).vec,9)), -- line 10
87 slv(to_unsigned(INTMAP( 9).vec,9)), -- line 9
88 slv(to_unsigned(INTMAP( 8).vec,9)), -- line 8
89 slv(to_unsigned(INTMAP( 7).vec,9)), -- line 7
90 slv(to_unsigned(INTMAP( 6).vec,9)), -- line 6
91 slv(to_unsigned(INTMAP( 5).vec,9)), -- line 5
92 slv(to_unsigned(INTMAP( 4).vec,9)), -- line 4
93 slv(to_unsigned(INTMAP( 3).vec,9)), -- line 3
94 slv(to_unsigned(INTMAP( 2).vec,9)), -- line 2
95 slv(to_unsigned(INTMAP( 1).vec,9)), -- line 1
96 slv(to_unsigned( 0,9)) -- line 0 (always 0 !!)
97 );
98
99-- attribute PRIORITY_EXTRACT : string;
100-- attribute PRIORITY_EXTRACT of EI_LINE : signal is "force";
101
102begin
103
104 EI_LINE <= "1111" when EI_REQ(15)='1' else
105 "1110" when EI_REQ(14)='1' else
106 "1101" when EI_REQ(13)='1' else
107 "1100" when EI_REQ(12)='1' else
108 "1011" when EI_REQ(11)='1' else
109 "1010" when EI_REQ(10)='1' else
110 "1001" when EI_REQ( 9)='1' else
111 "1000" when EI_REQ( 8)='1' else
112 "0111" when EI_REQ( 7)='1' else
113 "0110" when EI_REQ( 6)='1' else
114 "0101" when EI_REQ( 5)='1' else
115 "0100" when EI_REQ( 4)='1' else
116 "0011" when EI_REQ( 3)='1' else
117 "0010" when EI_REQ( 2)='1' else
118 "0001" when EI_REQ( 1)='1' else
119 "0000";
120
121 proc_line: process (CLK)
122 begin
123 if rising_edge(CLK) then
124 R_LINE <= EI_LINE;
125 end if;
126 end process proc_line;
127
128 -- Note: EI_ACKM comes one cycle after vector is latched ! Therefore
129 -- - use EI_LINE to select vector to send to EI_PRI and EI_VECT
130 -- - use R_LINE to select EI_ACM line for acknowledge
131 proc_intmap : process (EI_LINE, EI_ACKM, R_LINE)
132 variable ilinecur : integer := 0;
133 variable ilinelst : integer := 0;
134 variable iei_ack : slv16 := (others=>'0');
135 begin
136
137 ilinecur := to_integer(unsigned(EI_LINE));
138 ilinelst := to_integer(unsigned(R_LINE));
139
140 -- send info of currently highest priority request
141 EI_PRI <= conf_intp(ilinecur);
142 EI_VECT <= conf_intv(ilinecur)(8 downto 2);
143
144 -- route acknowledge back to winner line of last cycle
145 iei_ack := (others=>'0');
146 if EI_ACKM = '1' then
147 iei_ack(ilinelst) := '1';
148 end if;
149 EI_ACK <= iei_ack(EI_ACK'range);
150
151 end process proc_intmap;
152
153end syn;
intv_type :=( slv( to_unsigned( INTMAP( 15).vec, 9) ), slv( to_unsigned( INTMAP( 14).vec, 9) ), slv( to_unsigned( INTMAP( 13).vec, 9) ), slv( to_unsigned( INTMAP( 12).vec, 9) ), slv( to_unsigned( INTMAP( 11).vec, 9) ), slv( to_unsigned( INTMAP( 10).vec, 9) ), slv( to_unsigned( INTMAP( 9).vec, 9) ), slv( to_unsigned( INTMAP( 8).vec, 9) ), slv( to_unsigned( INTMAP( 7).vec, 9) ), slv( to_unsigned( INTMAP( 6).vec, 9) ), slv( to_unsigned( INTMAP( 5).vec, 9) ), slv( to_unsigned( INTMAP( 4).vec, 9) ), slv( to_unsigned( INTMAP( 3).vec, 9) ), slv( to_unsigned( INTMAP( 2).vec, 9) ), slv( to_unsigned( INTMAP( 1).vec, 9) ), slv( to_unsigned( 0, 9) )) conf_intv
Definition: ib_intmap.vhd:80
slv4 :=( others => '0') EI_LINE
Definition: ib_intmap.vhd:55
( 15 downto 0) slv3 intp_type
Definition: ib_intmap.vhd:58
slv4 :=( others => '0') R_LINE
Definition: ib_intmap.vhd:56
( 15 downto 0) slv9 intv_type
Definition: ib_intmap.vhd:59
intp_type :=( slv( to_unsigned( INTMAP( 15).pri, 3) ), slv( to_unsigned( INTMAP( 14).pri, 3) ), slv( to_unsigned( INTMAP( 13).pri, 3) ), slv( to_unsigned( INTMAP( 12).pri, 3) ), slv( to_unsigned( INTMAP( 11).pri, 3) ), slv( to_unsigned( INTMAP( 10).pri, 3) ), slv( to_unsigned( INTMAP( 9).pri, 3) ), slv( to_unsigned( INTMAP( 8).pri, 3) ), slv( to_unsigned( INTMAP( 7).pri, 3) ), slv( to_unsigned( INTMAP( 6).pri, 3) ), slv( to_unsigned( INTMAP( 5).pri, 3) ), slv( to_unsigned( INTMAP( 4).pri, 3) ), slv( to_unsigned( INTMAP( 3).pri, 3) ), slv( to_unsigned( INTMAP( 2).pri, 3) ), slv( to_unsigned( INTMAP( 1).pri, 3) ), slv( to_unsigned( 0, 3) )) conf_intp
Definition: ib_intmap.vhd:61
out EI_PRI slv3
Definition: ib_intmap.vhd:48
INTMAP intmap_array_type := intmap_array_init
Definition: ib_intmap.vhd:42
out EI_VECT slv9_2
Definition: ib_intmap.vhd:50
in CLK slbit
Definition: ib_intmap.vhd:44
in EI_REQ slv16_1
Definition: ib_intmap.vhd:45
out EI_ACK slv16_1
Definition: ib_intmap.vhd:47
in EI_ACKM slbit
Definition: ib_intmap.vhd:46
Definition: iblib.vhd:33
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 8 downto 2) slv9_2
Definition: slvtypes.vhd:65
std_logic_vector( 15 downto 1) slv16_1
Definition: slvtypes.vhd:67
std_logic_vector( 8 downto 0) slv9
Definition: slvtypes.vhd:41
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector slv
Definition: slvtypes.vhd:31