19use ieee.std_logic_1164.
all;
25pure function cram_delay(clk_mhz : positive;
26 delay_ps : positive) return positive;
27pure function cram_read0delay(clk_mhz : positive) return positive;
28pure function cram_read1delay(clk_mhz : positive) return positive;
29pure function cram_writedelay(clk_mhz : positive) return positive;
88pure function cram_delay(
92 variable period_ps : natural := 0;
94 period_ps := 1000000 / clk_mhz;
95 return (delay_ps + period_ps - 10) / period_ps;
96end function cram_delay;
99pure function cram_read0delay(
104end function cram_read0delay;
107pure function cram_read1delay(
112end function cram_read1delay;
115pure function cram_writedelay(
120end function cram_writedelay;
positive := 80000 cram_read0delay_ps
positive := 30000 cram_read1delay_ps
positive := 75000 cram_writedelay_ps
std_logic_vector( 22 downto 0) slv23
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 31 downto 0) slv32
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 21 downto 0) slv22
std_logic_vector( 1 downto 0) slv2