w11 - vhd 0.794
W11 CPU core and support modules
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nxcramlib.vhd
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1-- $Id: nxcramlib.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Package Name: nxcramlib
7-- Description: Nexys 2/3 CRAM controllers
8--
9-- Dependencies: -
10-- Tool versions: ise 11.4-14.7; viv 2014.4-2016.2; ghdl 0.26-0.33
11--
12-- Revision History:
13-- Date Rev Version Comment
14-- 2016-07-16 788 1.1 add cram_(read0|read1|write)delay functions
15-- 2011-11-26 433 1.0 Initial version (extracted from nexys2lib)
16------------------------------------------------------------------------------
17
18library ieee;
19use ieee.std_logic_1164.all;
20
21use work.slvtypes.all;
22
23package nxcramlib is
24
25pure function cram_delay(clk_mhz : positive;
26 delay_ps : positive) return positive;
27pure function cram_read0delay(clk_mhz : positive) return positive;
28pure function cram_read1delay(clk_mhz : positive) return positive;
29pure function cram_writedelay(clk_mhz : positive) return positive;
30
31constant cram_read0delay_ps : positive := 80000; -- initial read delay
32constant cram_read1delay_ps : positive := 30000; -- page read delay
33constant cram_writedelay_ps : positive := 75000; -- write delay
34
35component nx_cram_dummy is -- CRAM protection dummy
36 port (
37 O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
38 O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
39 O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
40 O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
41 O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
42 O_MEM_CLK : out slbit; -- cram: clock
43 O_MEM_CRE : out slbit; -- cram: command register enable
44 I_MEM_WAIT : in slbit; -- cram: mem wait
45 O_MEM_ADDR : out slv23; -- cram: address lines
46 IO_MEM_DATA : inout slv16 -- cram: data lines
47 );
48end component;
49
50component nx_cram_memctl_as is -- CRAM controller (async+page mode)
51 generic (
52 READ0DELAY : positive := 4; -- read word 0 delay in clock cycles
53 READ1DELAY : positive := 2; -- read word 1 delay in clock cycles
54 WRITEDELAY : positive := 4); -- write delay in clock cycles
55 port (
56 CLK : in slbit; -- clock
57 RESET : in slbit; -- reset
58 REQ : in slbit; -- request
59 WE : in slbit; -- write enable
60 BUSY : out slbit; -- controller busy
61 ACK_R : out slbit; -- acknowledge read
62 ACK_W : out slbit; -- acknowledge write
63 ACT_R : out slbit; -- signal active read
64 ACT_W : out slbit; -- signal active write
65 ADDR : in slv22; -- address (32 bit word address)
66 BE : in slv4; -- byte enable
67 DI : in slv32; -- data in (memory view)
68 DO : out slv32; -- data out (memory view)
69 O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
70 O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
71 O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
72 O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
73 O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
74 O_MEM_CLK : out slbit; -- cram: clock
75 O_MEM_CRE : out slbit; -- cram: command register enable
76 I_MEM_WAIT : in slbit; -- cram: mem wait
77 O_MEM_ADDR : out slv23; -- cram: address lines
78 IO_MEM_DATA : inout slv16 -- cram: data lines
79 );
80end component;
81
82end package nxcramlib;
83
84-- ----------------------------------------------------------------------------
85package body nxcramlib is
86
87-- -------------------------------------
88pure function cram_delay( -- calculate delay in clock cycles
89 clk_mhz : positive; -- clock frequency in MHz
90 delay_ps : positive) -- delay in ps
91 return positive is
92 variable period_ps : natural := 0; -- clk period in ps
93begin
94 period_ps := 1000000 / clk_mhz;
95 return (delay_ps + period_ps - 10) / period_ps;
96end function cram_delay;
97
98-- -------------------------------------
99pure function cram_read0delay( -- read0 delay in clock cycles
100 clk_mhz : positive) -- clock frequency in MHz
101 return positive is
102begin
103 return cram_delay(clk_mhz, cram_read0delay_ps);
104end function cram_read0delay;
105
106-- -------------------------------------
107pure function cram_read1delay( -- read1 delay in clock cycles
108 clk_mhz : positive) -- clock frequency in MHz
109 return positive is
110begin
111 return cram_delay(clk_mhz, cram_read1delay_ps);
112end function cram_read1delay;
113
114-- -------------------------------------
115pure function cram_writedelay( -- write delay in clock cycles
116 clk_mhz : positive) -- clock frequency in MHz
117 return positive is
118begin
119 return cram_delay(clk_mhz, cram_writedelay_ps);
120end function cram_writedelay;
121
122end package body nxcramlib;
out O_MEM_WE_N slbit
out O_MEM_CE_N slbit
in I_MEM_WAIT slbit
out O_MEM_OE_N slbit
out O_MEM_CLK slbit
out O_MEM_ADV_N slbit
out O_MEM_ADDR slv23
out O_MEM_BE_N slv2
inout IO_MEM_DATA slv16
out O_MEM_CRE slbit
READ0DELAY positive := 4
WRITEDELAY positive := 4
inout IO_MEM_DATA slv16
READ1DELAY positive := 2
positive := 80000 cram_read0delay_ps
Definition: nxcramlib.vhd:31
positive := 30000 cram_read1delay_ps
Definition: nxcramlib.vhd:32
positive := 75000 cram_writedelay_ps
Definition: nxcramlib.vhd:33
std_logic_vector( 22 downto 0) slv23
Definition: slvtypes.vhd:56
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic_vector( 21 downto 0) slv22
Definition: slvtypes.vhd:55
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34