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W11 CPU core and support modules
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nx_cram_dummy.vhd
Go to the documentation of this file.
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-- $Id: nx_cram_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: nx_cram_dummy - syn
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-- Description: nexys2/3: CRAM protection dummy
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: ise 11.4-14.7; viv 2014.4; ghdl 0.26-0.31
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-11-26 433 1.2 renamed from n2_cram_dummy
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-- 2011-11-23 432 1.1 remove O_FLA_CE_N port
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-- 2010-05-28 295 1.0.1 use _ADV_N
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-- 2010-05-21 292 1.0 Initial version
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------------------------------------------------------------------------------
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library
ieee
;
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use
ieee.std_logic_1164.
all
;
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use
work.
slvtypes
.
all
;
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entity
nx_cram_dummy
is
-- CRAM protection dummy
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port
(
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O_MEM_CE_N
:
out
slbit
;
-- cram: chip enable (act.low)
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O_MEM_BE_N
:
out
slv2
;
-- cram: byte enables (act.low)
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O_MEM_WE_N
:
out
slbit
;
-- cram: write enable (act.low)
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O_MEM_OE_N
:
out
slbit
;
-- cram: output enable (act.low)
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O_MEM_ADV_N
:
out
slbit
;
-- cram: address valid (act.low)
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O_MEM_CLK
:
out
slbit
;
-- cram: clock
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O_MEM_CRE
:
out
slbit
;
-- cram: command register enable
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I_MEM_WAIT
:
in
slbit
;
-- cram: mem wait
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O_MEM_ADDR
:
out
slv23
;
-- cram: address lines
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IO_MEM_DATA
:
inout
slv16
-- cram: data lines
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)
;
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end
nx_cram_dummy
;
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architecture
syn
of
nx_cram_dummy
is
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begin
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O_MEM_CE_N
<=
'
1
'
;
-- disable cram chip
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O_MEM_BE_N
<=
"11"
;
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O_MEM_WE_N
<=
'
1
'
;
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O_MEM_OE_N
<=
'
1
'
;
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O_MEM_ADV_N
<=
'
1
'
;
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O_MEM_CLK
<=
'
0
'
;
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O_MEM_CRE
<=
'
0
'
;
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O_MEM_ADDR
<=
(
others
=
>
'
0
'
)
;
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IO_MEM_DATA
<=
(
others
=
>
'
0
'
)
;
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end
syn
;
nx_cram_dummy.syn
Definition:
nx_cram_dummy.vhd:42
nx_cram_dummy
Definition:
nx_cram_dummy.vhd:26
nx_cram_dummy.O_MEM_WE_N
out O_MEM_WE_N slbit
Definition:
nx_cram_dummy.vhd:30
nx_cram_dummy.O_MEM_CE_N
out O_MEM_CE_N slbit
Definition:
nx_cram_dummy.vhd:28
nx_cram_dummy.I_MEM_WAIT
in I_MEM_WAIT slbit
Definition:
nx_cram_dummy.vhd:35
nx_cram_dummy.O_MEM_OE_N
out O_MEM_OE_N slbit
Definition:
nx_cram_dummy.vhd:31
nx_cram_dummy.O_MEM_CLK
out O_MEM_CLK slbit
Definition:
nx_cram_dummy.vhd:33
nx_cram_dummy.O_MEM_ADV_N
out O_MEM_ADV_N slbit
Definition:
nx_cram_dummy.vhd:32
nx_cram_dummy.O_MEM_ADDR
out O_MEM_ADDR slv23
Definition:
nx_cram_dummy.vhd:36
nx_cram_dummy.O_MEM_BE_N
out O_MEM_BE_N slv2
Definition:
nx_cram_dummy.vhd:29
nx_cram_dummy.IO_MEM_DATA
inout IO_MEM_DATA slv16
Definition:
nx_cram_dummy.vhd:38
nx_cram_dummy.O_MEM_CRE
out O_MEM_CRE slbit
Definition:
nx_cram_dummy.vhd:34
slvtypes
Definition:
slvtypes.vhd:28
slvtypes.slv23
std_logic_vector( 22 downto 0) slv23
Definition:
slvtypes.vhd:56
slvtypes.slv16
std_logic_vector( 15 downto 0) slv16
Definition:
slvtypes.vhd:48
slvtypes.slbit
std_logic slbit
Definition:
slvtypes.vhd:30
slvtypes.slv2
std_logic_vector( 1 downto 0) slv2
Definition:
slvtypes.vhd:34
bplib
nxcramlib
nx_cram_dummy.vhd
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