20use ieee.std_logic_1164.
all;
21use ieee.numeric_std.
all;
58 proc_regs:
process (
CLK)
61 if rising_edge(CLK) then
71 if R_COL(2) = '1' then
79 end process proc_regs;
out PAD slv( DWIDTH- 1 downto 0)
in DO slv( DWIDTH- 1 downto 0)
slv3 :=( others => '0') RGB1
slv3 :=( others => '0') RGB0
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 2 downto 0) slv3
std_logic_vector( 1 downto 0) slv2