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W11 CPU core and support modules
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rgbdrv_3x2mux.vhd
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1-- $Id: rgbdrv_3x2mux.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: rgbdrv_3x2mux - syn
7-- Description: rgbled driver: mux three 2bit inputs
8--
9-- Dependencies: xlib/iob_reg_o_gen
10-- Test bench: -
11-- Target Devices: generic
12-- Tool versions: viv 2017.2-2018.2; ghdl 0.34
13--
14-- Revision History:
15-- Date Rev Version Comment
16-- 2018-08-11 1038 1.0 Initial version (derived from rgbdrv_3x4mux)
17------------------------------------------------------------------------------
18
19library ieee;
20use ieee.std_logic_1164.all;
21use ieee.numeric_std.all;
22
23use work.slvtypes.all;
24use work.xlib.all;
25
26entity rgbdrv_3x2mux is -- rgbled driver: mux three 2bit inputs
27 port (
28 CLK : in slbit; -- clock
29 RESET : in slbit := '0'; -- reset
30 CE_USEC : in slbit; -- 1 us clock enable
31 DATR : in slv2; -- red data
32 DATG : in slv2; -- green data
33 DATB : in slv2; -- blue data
34 O_RGBLED0 : out slv3; -- pad-o: rgb led 0
35 O_RGBLED1 : out slv3 -- pad-o: rgb led 1
36 );
38
39
40architecture syn of rgbdrv_3x2mux is
41
42 signal R_LED : slv4 := "0001"; -- keep 4 states to keep brightness !
43 signal R_COL : slv3 := "001";
44 signal R_DIM : slbit := '1';
45
46 signal RGB0 : slv3 := (others=>'0');
47 signal RGB1 : slv3 := (others=>'0');
48
49begin
50
51 IOB_RGB0: iob_reg_o_gen
52 generic map (DWIDTH => 3)
53 port map (CLK => CLK, CE => '1', DO => RGB0, PAD => O_RGBLED0);
54 IOB_RGB1: iob_reg_o_gen
55 generic map (DWIDTH => 3)
56 port map (CLK => CLK, CE => '1', DO => RGB1, PAD => O_RGBLED1);
57
58 proc_regs: process (CLK)
59 begin
60
61 if rising_edge(CLK) then
62 if RESET = '1' then
63 R_LED <= "0001";
64 R_COL <= "001";
65 R_DIM <= '1';
66 else
67 if CE_USEC = '1' then
68 R_DIM <= not R_DIM;
69 if R_DIM = '1' then
70 R_COL <= R_COL(1) & R_COL(0) & R_COL(2);
71 if R_COL(2) = '1' then
72 R_LED <= R_LED(2) & R_LED(1) & R_LED(0) & R_LED(3);
73 end if;
74 end if;
75 end if;
76 end if;
77 end if;
78
79 end process proc_regs;
80
81 proc_mux: process (R_DIM, R_COL, R_LED, DATR, DATG, DATB)
82 begin
83 RGB0(0) <= (not R_DIM) and R_COL(0) and R_LED(0) and DATR(0);
84 RGB0(1) <= (not R_DIM) and R_COL(1) and R_LED(0) and DATG(0);
85 RGB0(2) <= (not R_DIM) and R_COL(2) and R_LED(0) and DATB(0);
86
87 RGB1(0) <= (not R_DIM) and R_COL(0) and R_LED(1) and DATR(1);
88 RGB1(1) <= (not R_DIM) and R_COL(1) and R_LED(1) and DATG(1);
89 RGB1(2) <= (not R_DIM) and R_COL(2) and R_LED(1) and DATB(1);
90 end process proc_mux;
91
92end syn;
in CE slbit := '1'
out PAD slv( DWIDTH- 1 downto 0)
in CLK slbit
in DO slv( DWIDTH- 1 downto 0)
DWIDTH positive := 16
slbit := '1' R_DIM
slv3 := "001" R_COL
slv3 :=( others => '0') RGB1
slv3 :=( others => '0') RGB0
slv4 := "0001" R_LED
in CE_USEC slbit
in CLK slbit
out O_RGBLED0 slv3
in RESET slbit := '0'
out O_RGBLED1 slv3
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
Definition: xlib.vhd:35