31use ieee.std_logic_1164.
all;
83component iob_reg_io
is
88 PULL :
string :=
"NONE");
91 CEI :
in slbit := '
1';
92 CEO :
in slbit := '
1';
106 PULL :
string :=
"NONE");
120 PULL :
string :=
"NONE");
129component iob_oddr2_simple
is
131 ALIGN :
string :=
"NONE";
132 INIT : slbit := '
0');
135 CE :
in slbit := '
1';
142component iob_io_gen
is
144 DWIDTH :
positive :=
16;
145 PULL :
string :=
"NONE");
148 DI :
out slv(DWIDTH
-1 downto 0);
149 DO :
in slv(DWIDTH
-1 downto 0);
150 PAD :
inout slv(DWIDTH
-1 downto 0)
154component iob_keeper
is
214component s7_cmt_sfs_3
is
216 VCO_DIVIDE :
positive :=
1;
217 VCO_MULTIPLY :
positive :=
1;
218 OUT0_DIVIDE :
positive :=
1;
219 OUT1_DIVIDE :
positive :=
1;
220 OUT2_DIVIDE :
positive :=
1;
221 CLKIN_PERIOD :
real :=
10.
0;
222 CLKIN_JITTER :
real :=
0.
01;
223 STARTUP_WAIT :
boolean := false;
224 GEN_TYPE :
string :=
"PLL");
CLKFX_DIVIDE positive := 1
CLKFX_MULTIPLY positive := 1
CLKIN_PERIOD real := 20.0
inout PAD slv( DWIDTH- 1 downto 0)
in PAD slv( DWIDTH- 1 downto 0)
out DI slv( DWIDTH- 1 downto 0)
inout PAD slv( DWIDTH- 1 downto 0)
in DO slv( DWIDTH- 1 downto 0)
out DI slv( DWIDTH- 1 downto 0)
out PAD slv( DWIDTH- 1 downto 0)
in DO slv( DWIDTH- 1 downto 0)
CLKIN_PERIOD real := 10.0
CLKIN_JITTER real := 0.01
STARTUP_WAIT boolean := false
VCO_MULTIPLY positive := 1
CLKIN_PERIOD real := 10.0
OUT1_DIVIDE positive := 1
CLKIN_JITTER real := 0.01
OUT0_DIVIDE positive := 1
STARTUP_WAIT boolean := false
VCO_MULTIPLY positive := 1
CLKIN_PERIOD real := 10.0
CLKIN_JITTER real := 0.01
STARTUP_WAIT boolean := false
VCO_MULTIPLY positive := 1
VCO_MULTIPLY positive := 1
std_logic_vector( 31 downto 0) slv32