w11 - vhd 0.794
W11 CPU core and support modules
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xlib.vhd
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1-- $Id: xlib.vhd 1247 2022-07-06 07:04:33Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2007-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Package Name: xlib
7-- Description: Xilinx specific components
8--
9-- Dependencies: -
10-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
11-- Revision History:
12-- Date Rev Version Comment
13-- 2022-07-05 1247 1.1.2 add bufg_unisim
14-- 2018-11-18 1072 1.1.1 add s7_cmt_sfs_3 and s7_cmt_sfs_2
15-- 2018-11-03 1064 1.1 add sfs_gsim_core
16-- 2016-04-02 758 1.0.11 add usr_access_unisim
17-- 2013-10-06 538 1.0.10 add s6_cmt_sfs
18-- 2013-09-28 535 1.0.9 add s7_cmt_sfs
19-- 2011-11-24 432 1.0.8 add iob_oddr2_simple
20-- 2011-11-17 426 1.0.7 rename dcm_sp_sfs -> dcm_sfs; remove family generic
21-- 2011-11-10 423 1.0.6 add family generic for dcm_sp_sfs
22-- 2010-11-07 337 1.0.5 add dcm_sp_sfs
23-- 2008-05-23 149 1.0.4 add iob_io(_gen)
24-- 2008-05-22 148 1.0.3 add iob_keeper(_gen);
25-- 2008-05-18 147 1.0.2 add PULL generic to iob_reg_io(_gen)
26-- 2007-12-16 101 1.0.1 add INIT generic ports
27-- 2007-12-08 100 1.0 Initial version
28------------------------------------------------------------------------------
29
30library ieee;
31use ieee.std_logic_1164.all;
32
33use work.slvtypes.all;
34
35package xlib is
36
37component iob_reg_i is -- registered IOB, input
38 generic (
39 INIT : slbit := '0'); -- initial state
40 port (
41 CLK : in slbit; -- clock
42 CE : in slbit := '1'; -- clock enable
43 DI : out slbit; -- input data
44 PAD : in slbit -- i/o pad
45 );
46end component;
47
48component iob_reg_i_gen is -- registered IOB, input, vector
49 generic (
50 DWIDTH : positive := 16; -- data port width
51 INIT : slbit := '0'); -- initial state
52 port (
53 CLK : in slbit; -- clock
54 CE : in slbit := '1'; -- clock enable
55 DI : out slv(DWIDTH-1 downto 0); -- input data
56 PAD : in slv(DWIDTH-1 downto 0) -- i/o pad
57 );
58end component;
59
60component iob_reg_o is -- registered IOB, output
61 generic (
62 INIT : slbit := '0'); -- initial state
63 port (
64 CLK : in slbit; -- clock
65 CE : in slbit := '1'; -- clock enable
66 DO : in slbit; -- output data
67 PAD : out slbit -- i/o pad
68 );
69end component;
70
71component iob_reg_o_gen is -- registered IOB, output, vector
72 generic (
73 DWIDTH : positive := 16; -- data port width
74 INIT : slbit := '0'); -- initial state
75 port (
76 CLK : in slbit; -- clock
77 CE : in slbit := '1'; -- clock enable
78 DO : in slv(DWIDTH-1 downto 0); -- output data
79 PAD : out slv(DWIDTH-1 downto 0) -- i/o pad
80 );
81end component;
82
83component iob_reg_io is -- registered IOB, in/output
84 generic (
85 INITI : slbit := '0'; -- initial state ( in flop)
86 INITO : slbit := '0'; -- initial state (out flop)
87 INITE : slbit := '0'; -- initial state ( oe flop)
88 PULL : string := "NONE"); -- pull-up,-down or keeper
89 port (
90 CLK : in slbit; -- clock
91 CEI : in slbit := '1'; -- clock enable ( in flops)
92 CEO : in slbit := '1'; -- clock enable (out flops)
93 OE : in slbit; -- output enable
94 DI : out slbit; -- input data (read from pad)
95 DO : in slbit; -- output data (write to pad)
96 PAD : inout slbit -- i/o pad
97 );
98end component;
99
100component iob_reg_io_gen is -- registered IOB, in/output, vector
101 generic (
102 DWIDTH : positive := 16; -- data port width
103 INITI : slbit := '0'; -- initial state ( in flop)
104 INITO : slbit := '0'; -- initial state (out flop)
105 INITE : slbit := '0'; -- initial state ( oe flop)
106 PULL : string := "NONE"); -- pull-up,-down or keeper
107 port (
108 CLK : in slbit; -- clock
109 CEI : in slbit := '1'; -- clock enable ( in flops)
110 CEO : in slbit := '1'; -- clock enable (out flops)
111 OE : in slbit; -- output enable
112 DI : out slv(DWIDTH-1 downto 0); -- input data (read from pad)
113 DO : in slv(DWIDTH-1 downto 0); -- output data (write to pad)
114 PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad
115 );
116end component;
117
118component iob_io is -- un-registered IOB, in/output
119 generic (
120 PULL : string := "NONE"); -- pull-up,-down or keeper
121 port (
122 OE : in slbit; -- output enable
123 DI : out slbit; -- input data (read from pad)
124 DO : in slbit; -- output data (write to pad)
125 PAD : inout slbit -- i/o pad
126 );
127end component;
128
129component iob_oddr2_simple is -- DDR2 output I/O pad
130 generic (
131 ALIGN : string := "NONE"; -- ddr_alignment
132 INIT : slbit := '0'); -- initial state
133 port (
134 CLK : in slbit; -- clock
135 CE : in slbit := '1'; -- clock enable
136 DO0 : in slbit; -- output data
137 DO1 : in slbit; -- output data
138 PAD : out slbit -- i/o pad
139 );
140end component;
141
142component iob_io_gen is -- un-registered IOB, in/output, vector
143 generic (
144 DWIDTH : positive := 16; -- data port width
145 PULL : string := "NONE"); -- pull-up,-down or keeper
146 port (
147 OE : in slbit; -- output enable
148 DI : out slv(DWIDTH-1 downto 0); -- input data (read from pad)
149 DO : in slv(DWIDTH-1 downto 0); -- output data (write to pad)
150 PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad
151 );
152end component;
153
154component iob_keeper is -- keeper for IOB
155 port (
156 PAD : inout slbit -- i/o pad
157 );
158end component;
159
160component iob_keeper_gen is -- keeper for IOB, vector
161 generic (
162 DWIDTH : positive := 16); -- data port width
163 port (
164 PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad
165 );
166end component;
167
168component dcm_sfs is -- DCM for simple frequency synthesis
169 generic (
170 CLKFX_DIVIDE : positive := 2; -- FX clock divide (1-32)
171 CLKFX_MULTIPLY : positive := 2; -- FX clock multiply (2-32) (1->no DCM)
172 CLKIN_PERIOD : real := 20.0); -- CLKIN period (def is 20.0 ns)
173 port (
174 CLKIN : in slbit; -- clock input
175 CLKFX : out slbit; -- clock output (synthesized freq.)
176 LOCKED : out slbit -- dcm locked
177 );
178end component;
179
180component s7_cmt_sfs is -- 7-Series CMT for simple freq. synth.
181 generic (
182 VCO_DIVIDE : positive := 1; -- vco clock divide
183 VCO_MULTIPLY : positive := 1; -- vco clock multiply
184 OUT_DIVIDE : positive := 1; -- output divide
185 CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
186 CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
187 STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
188 GEN_TYPE : string := "PLL"); -- PLL or MMCM
189 port (
190 CLKIN : in slbit; -- clock input
191 CLKFX : out slbit; -- clock output (synthesized freq.)
192 LOCKED : out slbit -- pll/mmcm locked
193 );
194end component;
195
196component s7_cmt_sfs_2 is -- 7-Series CMT for dual freq. synth.
197 generic (
198 VCO_DIVIDE : positive := 1; -- vco clock divide
199 VCO_MULTIPLY : positive := 1; -- vco clock multiply
200 OUT0_DIVIDE : positive := 1; -- output 0 divide
201 OUT1_DIVIDE : positive := 1; -- output 1 divide
202 CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
203 CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
204 STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
205 GEN_TYPE : string := "PLL"); -- PLL or MMCM
206 port (
207 CLKIN : in slbit; -- clock input
208 CLKOUT0 : out slbit; -- clock output 0
209 CLKOUT1 : out slbit; -- clock output 1
210 LOCKED : out slbit -- pll/mmcm locked
211 );
212end component;
213
214component s7_cmt_sfs_3 is -- 7-Series CMT for tripple freq. synth.
215 generic (
216 VCO_DIVIDE : positive := 1; -- vco clock divide
217 VCO_MULTIPLY : positive := 1; -- vco clock multiply
218 OUT0_DIVIDE : positive := 1; -- output 0 divide
219 OUT1_DIVIDE : positive := 1; -- output 1 divide
220 OUT2_DIVIDE : positive := 1; -- output 2 divide
221 CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
222 CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
223 STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
224 GEN_TYPE : string := "PLL"); -- PLL or MMCM
225 port (
226 CLKIN : in slbit; -- clock input
227 CLKOUT0 : out slbit; -- clock output 0
228 CLKOUT1 : out slbit; -- clock output 1
229 CLKOUT2 : out slbit; -- clock output 2
230 LOCKED : out slbit -- pll/mmcm locked
231 );
232end component;
233
234component s6_cmt_sfs is -- Spartan-6 CMT for simple freq. synth.
235 generic (
236 VCO_DIVIDE : positive := 1; -- vco clock divide
237 VCO_MULTIPLY : positive := 1; -- vco clock multiply
238 OUT_DIVIDE : positive := 1; -- output divide
239 CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
240 CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
241 STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
242 GEN_TYPE : string := "PLL"); -- PLL or DCM
243 port (
244 CLKIN : in slbit; -- clock input
245 CLKFX : out slbit; -- clock output (synthesized freq.)
246 LOCKED : out slbit -- pll/mmcm locked
247 );
248end component;
249
250component sfs_gsim_core is -- frequency synthesis for simulation
251 generic (
252 VCO_DIVIDE : positive := 1; -- vco clock divide
253 VCO_MULTIPLY : positive := 1; -- vco clock multiply
254 OUT_DIVIDE : positive := 1); -- output divide
255 port (
256 CLKIN : in slbit; -- clock input
257 CLKFX : out slbit; -- clock output (synthesized freq.)
258 LOCKED : out slbit -- clkin locked
259 );
260end component;
261
262component usr_access_unisim is -- wrapper for USR_ACCESS family
263 port (
264 DATA : out slv32 -- usr_access register value
265 );
266end component;
267
268component bufg_unisim is -- wrapper for bufg
269 port (
270 O : out std_ulogic; -- input
271 I : in std_ulogic -- output
272 );
273end component;
274
275end package xlib;
in I std_ulogic
Definition: bufg_unisim.vhd:29
out O std_ulogic
Definition: bufg_unisim.vhd:27
CLKFX_DIVIDE positive := 1
in CLKIN slbit
CLKFX_MULTIPLY positive := 1
out LOCKED slbit
CLKIN_PERIOD real := 20.0
out CLKFX slbit
inout PAD slv( DWIDTH- 1 downto 0)
DWIDTH positive := 16
in CE slbit := '1'
in PAD slv( DWIDTH- 1 downto 0)
INIT slbit := '0'
in CLK slbit
out DI slv( DWIDTH- 1 downto 0)
DWIDTH positive := 16
in PAD slbit
Definition: iob_reg_i.vhd:33
in CE slbit := '1'
Definition: iob_reg_i.vhd:30
INIT slbit := '0'
Definition: iob_reg_i.vhd:27
in CLK slbit
Definition: iob_reg_i.vhd:29
out DI slbit
Definition: iob_reg_i.vhd:31
in CEO slbit := '1'
in CEI slbit := '1'
INITO slbit := '0'
PULL string := "NONE"
INITE slbit := '0'
inout PAD slv( DWIDTH- 1 downto 0)
INITI slbit := '0'
in DO slv( DWIDTH- 1 downto 0)
out DI slv( DWIDTH- 1 downto 0)
DWIDTH positive := 16
in CE slbit := '1'
out PAD slv( DWIDTH- 1 downto 0)
INIT slbit := '0'
in CLK slbit
in DO slv( DWIDTH- 1 downto 0)
DWIDTH positive := 16
in CE slbit := '1'
Definition: iob_reg_o.vhd:30
out PAD slbit
Definition: iob_reg_o.vhd:33
INIT slbit := '0'
Definition: iob_reg_o.vhd:27
in CLK slbit
Definition: iob_reg_o.vhd:29
in DO slbit
Definition: iob_reg_o.vhd:31
VCO_DIVIDE positive := 1
GEN_TYPE string := "PLL"
CLKIN_PERIOD real := 10.0
OUT_DIVIDE positive := 1
in CLKIN slbit
CLKIN_JITTER real := 0.01
STARTUP_WAIT boolean := false
VCO_MULTIPLY positive := 1
out LOCKED slbit
out CLKFX slbit
VCO_DIVIDE positive := 1
GEN_TYPE string := "PLL"
out CLKOUT1 slbit
CLKIN_PERIOD real := 10.0
OUT1_DIVIDE positive := 1
out CLKOUT0 slbit
CLKIN_JITTER real := 0.01
OUT0_DIVIDE positive := 1
STARTUP_WAIT boolean := false
VCO_MULTIPLY positive := 1
out LOCKED slbit
VCO_DIVIDE positive := 1
GEN_TYPE string := "PLL"
CLKIN_PERIOD real := 10.0
OUT_DIVIDE positive := 1
in CLKIN slbit
CLKIN_JITTER real := 0.01
STARTUP_WAIT boolean := false
VCO_MULTIPLY positive := 1
out LOCKED slbit
out CLKFX slbit
VCO_DIVIDE positive := 1
OUT_DIVIDE positive := 1
in CLKIN slbit
VCO_MULTIPLY positive := 1
out LOCKED slbit
out CLKFX slbit
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector slv
Definition: slvtypes.vhd:31
Definition: xlib.vhd:35