23use ieee.std_logic_1164.
all;
51 constant f_vcomin_pll
: integer := 400;
52 constant f_vcomax_pll
: integer := 1000;
53 constant f_pdmin_pll
: integer := 19;
54 constant f_pdmax_pll
: integer := 375;
56 variable t_vco : Delay_length := 0 ns;
57 variable t_vcomin : Delay_length := 0 ns;
58 variable t_vcomax : Delay_length := 0 ns;
59 variable t_pd : Delay_length := 0 ns;
60 variable t_pdmin : Delay_length := 0 ns;
61 variable t_pdmax : Delay_length := 0 ns;
67 report "assert(GEN_TYPE='PLL' or GEN_TYPE='DCM')"
80 "assert(VCO_DIVIDE in 1:52 VCO_MULTIPLY in 1:64 OUT_DIVIDE in 1:128)"
84 t_vcomin := (1000 ns / f_vcomax_pll) - 1 ps;
85 t_vcomax := (1000 ns / f_vcomin_pll) + 1 ps;
86 t_pdmin := (1000 ns / f_pdmax_pll) - 1 ps;
87 t_pdmax := (1000 ns / f_pdmin_pll) + 1 ps;
93 if t_vco<t_vcomin or t_vco>t_vcomax then
94 report "assert(VCO frequency out of range)"
98 if t_pd<t_pdmin or t_pd>t_pdmax then
99 report "assert(PD frequency out of range)"
112 "assert(VCO_DIVIDE in 1:32 VCO_MULTIPLY in 2:32 OUT_DIVIDE=1)"
120 end process proc_init;
CLKIN_PERIOD real := 10.0
CLKIN_JITTER real := 0.01
STARTUP_WAIT boolean := false
VCO_MULTIPLY positive := 1
VCO_MULTIPLY positive := 1