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W11 CPU core and support modules
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s6_cmt_sfs_gsim.vhd
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1-- $Id: s6_cmt_sfs_gsim.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2013-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: s6_cmt_sfs - sim
7-- Description: Spartan-6 CMT for simple frequency synthesis
8-- simple vhdl model, without Xilinx UNISIM primitives
9--
10-- Dependencies: -
11-- Test bench: -
12-- Target Devices: generic Spartan-6
13-- Tool versions: xst 14.5-14.7; ghdl 0.29-0.34
14--
15-- Revision History:
16-- Date Rev Version Comment
17-- 2018-11-03 1065 1.1 use sfs_gsim_core
18-- 2016-08-18 799 1.0.1 remove 'assert false' from report statements
19-- 2013-10-06 538 1.0 Initial version (derived from s7_cmt_sfs_gsim)
20------------------------------------------------------------------------------
21
22library ieee;
23use ieee.std_logic_1164.all;
24
25use work.slvtypes.all;
26use work.xlib.all;
27
28entity s6_cmt_sfs is -- Spartan-6 CMT for simple freq. synth.
29 generic (
30 VCO_DIVIDE : positive := 1; -- vco clock divide
31 VCO_MULTIPLY : positive := 1; -- vco clock multiply
32 OUT_DIVIDE : positive := 1; -- output divide
33 CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
34 CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
35 STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
36 GEN_TYPE : string := "PLL"); -- PLL or MMCM
37 port (
38 CLKIN : in slbit; -- clock input
39 CLKFX : out slbit; -- clock output (synthesized freq.)
40 LOCKED : out slbit -- pll/mmcm locked
41 );
42end s6_cmt_sfs;
43
44
45architecture sim of s6_cmt_sfs is
46begin
47
48 proc_init : process
49
50 -- currently frequency limits taken from Spartan-6 speed grade -2
51 constant f_vcomin_pll: integer := 400;
52 constant f_vcomax_pll: integer := 1000;
53 constant f_pdmin_pll: integer := 19;
54 constant f_pdmax_pll: integer := 375;
55
56 variable t_vco : Delay_length := 0 ns;
57 variable t_vcomin : Delay_length := 0 ns;
58 variable t_vcomax : Delay_length := 0 ns;
59 variable t_pd : Delay_length := 0 ns;
60 variable t_pdmin : Delay_length := 0 ns;
61 variable t_pdmax : Delay_length := 0 ns;
62
63 begin
64
65 -- validate generics
66 if not (GEN_TYPE = "PLL" or GEN_TYPE = "DCM") then
67 report "assert(GEN_TYPE='PLL' or GEN_TYPE='DCM')"
68 severity failure;
69 end if;
70
71 if VCO_DIVIDE/=1 or VCO_MULTIPLY/=1 or OUT_DIVIDE/=1 then
72
73 if GEN_TYPE = "PLL" then
74 -- check DIV/MULT parameter range
75 if VCO_DIVIDE<1 or VCO_DIVIDE>52 or
76 VCO_MULTIPLY<1 or VCO_MULTIPLY>64 or
77 OUT_DIVIDE<1 or OUT_DIVIDE>128
78 then
79 report
80 "assert(VCO_DIVIDE in 1:52 VCO_MULTIPLY in 1:64 OUT_DIVIDE in 1:128)"
81 severity failure;
82 end if;
83 -- setup VCO and PD range check boundaries
84 t_vcomin := (1000 ns / f_vcomax_pll) - 1 ps;
85 t_vcomax := (1000 ns / f_vcomin_pll) + 1 ps;
86 t_pdmin := (1000 ns / f_pdmax_pll) - 1 ps;
87 t_pdmax := (1000 ns / f_pdmin_pll) + 1 ps;
88
89 -- now check whether VCO and PD frequency is in range
90 t_pd := (1 ps * (1000.0*CLKIN_PERIOD)) * VCO_DIVIDE;
91 t_vco := t_pd / VCO_MULTIPLY;
92
93 if t_vco<t_vcomin or t_vco>t_vcomax then
94 report "assert(VCO frequency out of range)"
95 severity failure;
96 end if;
97
98 if t_pd<t_pdmin or t_pd>t_pdmax then
99 report "assert(PD frequency out of range)"
100 severity failure;
101 end if;
102
103 end if; -- GEN_TYPE = "PLL"
104
105 if GEN_TYPE = "DCM" then
106 -- check DIV/MULT parameter range
107 if VCO_DIVIDE<1 or VCO_DIVIDE>32 or
108 VCO_MULTIPLY<2 or VCO_MULTIPLY>32 or
109 OUT_DIVIDE/=1
110 then
111 report
112 "assert(VCO_DIVIDE in 1:32 VCO_MULTIPLY in 2:32 OUT_DIVIDE=1)"
113 severity failure;
114 end if;
115 end if; -- GEN_TYPE = "MMCM"
116
117 end if; -- one factor /= 1
118
119 wait;
120 end process proc_init;
121
122 -- generate clock
123 SFS: sfs_gsim_core
124 generic map (
128 port map (
129 CLKIN => CLKIN,
130 CLKFX => CLKFX,
131 LOCKED => LOCKED
132 );
133
134end sim;
VCO_DIVIDE positive := 1
GEN_TYPE string := "PLL"
CLKIN_PERIOD real := 10.0
OUT_DIVIDE positive := 1
in CLKIN slbit
CLKIN_JITTER real := 0.01
STARTUP_WAIT boolean := false
VCO_MULTIPLY positive := 1
out LOCKED slbit
out CLKFX slbit
VCO_DIVIDE positive := 1
OUT_DIVIDE positive := 1
in CLKIN slbit
VCO_MULTIPLY positive := 1
out LOCKED slbit
out CLKFX slbit
std_logic slbit
Definition: slvtypes.vhd:30
Definition: xlib.vhd:35