w11 - vhd 0.794
W11 CPU core and support modules
Loading...
Searching...
No Matches
sramif_mig_nexys4d.vhd
Go to the documentation of this file.
1-- $Id: sramif_mig_nexys4d.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2018-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sramif_mig_nexys4d - syn
7-- Description: SRAM to DDR via MIG for nexys4d
8--
9-- Dependencies: bplib/mig/sramif2migui_core
10-- cdclib/cdc_pulse
11-- cdclib/cdc_value
12-- migui_nexys4d (generated core)
13-- Test bench: tb_tst_sram_nexys4d
14-- Target Devices: nexys4 DDRboard
15-- Tool versions: viv 2017.2; ghdl 0.34
16--
17-- Revision History:
18-- Date Rev Version Comment
19-- 2019-01-02 1101 1.0.1 Initial version
20-- 2018-12-30 1099 1.0 First draft (cloned from arty)
21--
22------------------------------------------------------------------------------
23
24library ieee;
25use ieee.std_logic_1164.all;
26use ieee.numeric_std.all;
27
28use work.slvtypes.all;
29use work.cdclib.all;
30use work.miglib.all;
31use work.miglib_nexys4d.all;
32
33entity sramif_mig_nexys4d is -- SRAM to DDR via MIG for nexyx4d
34 port (
35 CLK : in slbit; -- clock
36 RESET : in slbit; -- reset
37 REQ : in slbit; -- request
38 WE : in slbit; -- write enable
39 BUSY : out slbit; -- controller busy
40 ACK_R : out slbit; -- acknowledge read
41 ACK_W : out slbit; -- acknowledge write
42 ACT_R : out slbit; -- signal active read
43 ACT_W : out slbit; -- signal active write
44 ADDR : in slv20; -- address (32 bit word address)
45 BE : in slv4; -- byte enable
46 DI : in slv32; -- data in (memory view)
47 DO : out slv32; -- data out (memory view)
48 CLKMIG : in slbit; -- sys clock for mig core
49 CLKREF : in slbit; -- ref clock for mig core
50 TEMP : in slv12; -- xadc die temp for mig core
51 MONI : out sramif2migui_moni_type;-- monitor signals
52 DDR2_DQ : inout slv16; -- dram: data in/out
53 DDR2_DQS_P : inout slv2; -- dram: data strobe (diff-p)
54 DDR2_DQS_N : inout slv2; -- dram: data strobe (diff-n)
55 DDR2_ADDR : out slv13; -- dram: address
56 DDR2_BA : out slv3; -- dram: bank address
57 DDR2_RAS_N : out slbit; -- dram: row addr strobe (act.low)
58 DDR2_CAS_N : out slbit; -- dram: column addr strobe (act.low)
59 DDR2_WE_N : out slbit; -- dram: write enable (act.low)
60 DDR2_CK_P : out slv1; -- dram: clock (diff-p)
61 DDR2_CK_N : out slv1; -- dram: clock (diff-n)
62 DDR2_CKE : out slv1; -- dram: clock enable
63 DDR2_CS_N : out slv1; -- dram: chip select (act.low)
64 DDR2_DM : out slv2; -- dram: data input mask
65 DDR2_ODT : out slv1 -- dram: on-die termination
66 );
68
69
70architecture syn of sramif_mig_nexys4d is
71
72 signal MIG_BUSY : slbit := '0';
73
74 signal APP_RDY : slbit := '0';
75 signal APP_EN : slbit := '0';
76 signal APP_CMD : slv3 := (others=>'0');
77 signal APP_ADDR : slv(mig_mawidth-1 downto 0) := (others=>'0');
78 signal APP_WDF_RDY : slbit := '0';
79 signal APP_WDF_WREN : slbit := '0';
80 signal APP_WDF_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0');
81 signal APP_WDF_MASK : slv(mig_mwidth-1 downto 0) := (others=>'0');
82 signal APP_WDF_END : slbit := '0';
83 signal APP_RD_DATA_VALID : slbit := '0';
84 signal APP_RD_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0');
85 signal APP_RD_DATA_END : slbit := '0';
86
87 signal UI_CLK_SYNC_RST : slbit := '0';
88 signal INIT_CALIB_COMPLETE : slbit := '0';
89
90 signal SYS_RST : slbit := '0';
91 signal SYS_RST_BUSY : slbit := '0';
92
93 signal CLKMUI : slbit := '0';
94 signal TEMP_MUI : slv12 := (others=>'0'); -- xadc die temp; on CLKMUI
95
96begin
97
98 SR2MIG: sramif2migui_core -- SRAM to MIG iface -----------------
99 generic map (
100 BAWIDTH => mig_bawidth,
101 MAWIDTH => mig_mawidth)
102 port map (
103 CLK => CLK,
104 RESET => RESET,
105 REQ => REQ,
106 WE => WE,
107 BUSY => MIG_BUSY,
108 ACK_R => ACK_R,
109 ACK_W => ACK_W,
110 ACT_R => ACT_R,
111 ACT_W => ACT_W,
112 ADDR => ADDR,
113 BE => BE,
114 DI => DI,
115 DO => DO,
116 MONI => MONI,
117 UI_CLK => CLKMUI,
118 UI_CLK_SYNC_RST => UI_CLK_SYNC_RST,
119 INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE,
120 APP_RDY => APP_RDY,
121 APP_EN => APP_EN,
122 APP_CMD => APP_CMD,
123 APP_ADDR => APP_ADDR,
124 APP_WDF_RDY => APP_WDF_RDY,
125 APP_WDF_WREN => APP_WDF_WREN,
126 APP_WDF_DATA => APP_WDF_DATA,
127 APP_WDF_MASK => APP_WDF_MASK,
128 APP_WDF_END => APP_WDF_END,
129 APP_RD_DATA_VALID => APP_RD_DATA_VALID,
130 APP_RD_DATA => APP_RD_DATA,
131 APP_RD_DATA_END => APP_RD_DATA_END
132 );
133
134 CDC_SYSRST: cdc_pulse
135 generic map (
136 POUT_SINGLE => false,
137 BUSY_WACK => true)
138 port map (
139 CLKM => CLK,
140 RESET => '0',
141 CLKS => CLKMIG,
142 PIN => RESET,
144 POUT => SYS_RST
145 );
146
147 CDC_TEMP: cdc_value
148 generic map (
149 DWIDTH => TEMP'length)
150 port map (
151 CLKI => CLK,
152 CLKO => CLKMUI,
153 DI => TEMP,
154 DO => TEMP_MUI,
155 UPDT => open
156 );
157
158 MIG_CTL: migui_nexys4d
159 port map (
160 DDR2_DQ => DDR2_DQ,
164 DDR2_BA => DDR2_BA,
172 DDR2_DM => DDR2_DM,
175 APP_CMD => APP_CMD,
176 APP_EN => APP_EN,
184 APP_RDY => APP_RDY,
186 APP_SR_REQ => '0',
187 APP_REF_REQ => '0',
188 APP_ZQ_REQ => '0',
189 APP_SR_ACTIVE => open,
190 APP_REF_ACK => open,
191 APP_ZQ_ACK => open,
192 UI_CLK => CLKMUI,
195 SYS_CLK_I => CLKMIG,
196 CLK_REF_I => CLKREF,
199 );
200
202
203end syn;
in CLKM slbit
Definition: cdc_pulse.vhd:32
out BUSY slbit
Definition: cdc_pulse.vhd:36
out POUT slbit
Definition: cdc_pulse.vhd:38
in CLKS slbit
Definition: cdc_pulse.vhd:34
in PIN slbit
Definition: cdc_pulse.vhd:35
BUSY_WACK boolean := false
Definition: cdc_pulse.vhd:29
in RESET slbit := '0'
Definition: cdc_pulse.vhd:33
POUT_SINGLE boolean := false
Definition: cdc_pulse.vhd:28
out DO slv( DWIDTH- 1 downto 0)
Definition: cdc_value.vhd:34
in CLKO slbit
Definition: cdc_value.vhd:32
in DI slv( DWIDTH- 1 downto 0)
Definition: cdc_value.vhd:33
in CLKI slbit
Definition: cdc_value.vhd:31
out UPDT slbit
Definition: cdc_value.vhd:36
DWIDTH positive := 16
Definition: cdc_value.vhd:29
out APP_RD_DATA slv( mig_dwidth- 1 downto 0)
out APP_RD_DATA_VALID slbit
out APP_REF_ACK slbit
out APP_RD_DATA_END slbit
out DDR2_RAS_N slbit
inout DDR2_DQS_P slv2
inout DDR2_DQS_N slv2
in APP_WDF_MASK slv( mig_mwidth- 1 downto 0)
in DEVICE_TEMP_I slv12
inout DDR2_DQ slv16
out INIT_CALIB_COMPLETE slbit
out DDR2_WE_N slbit
out DDR2_CAS_N slbit
out APP_ZQ_ACK slbit
out DDR2_ADDR slv13
out APP_WDF_RDY slbit
in APP_WDF_WREN slbit
out APP_SR_ACTIVE slbit
in APP_ADDR slv( mig_mawidth- 1 downto 0)
in APP_WDF_DATA slv( mig_dwidth- 1 downto 0)
out UI_CLK_SYNC_RST slbit
std_logic_vector( 19 downto 0) slv20
Definition: slvtypes.vhd:53
std_logic_vector( 12 downto 0) slv13
Definition: slvtypes.vhd:45
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 11 downto 0) slv12
Definition: slvtypes.vhd:44
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 0 downto 0) slv1
Definition: slvtypes.vhd:33
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
std_logic_vector slv
Definition: slvtypes.vhd:31
slv( mig_dwidth- 1 downto 0) :=( others => '0') APP_RD_DATA
slv( mig_mawidth- 1 downto 0) :=( others => '0') APP_ADDR
slv3 :=( others => '0') APP_CMD
slv( mig_mwidth- 1 downto 0) :=( others => '0') APP_WDF_MASK
slv( mig_dwidth- 1 downto 0) :=( others => '0') APP_WDF_DATA
slv12 :=( others => '0') TEMP_MUI
out MONI sramif2migui_moni_type