w11 - vhd 0.794
W11 CPU core and support modules
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tb_cmoda7_core.vhd
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1-- $Id: tb_cmoda7_core.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: tb_cmoda7_core - sim
7-- Description: Test bench for cmoda7 - core device handling
8--
9-- Dependencies: -
10--
11-- To test: generic, any cmoda7 target
12--
13-- Target Devices: generic
14-- Tool versions: viv 2016.4; ghdl 0.34
15-- Revision History:
16-- Date Rev Version Comment
17-- 2017-06-04 906 1.0 Initial version (derived from tb_arty_core)
18------------------------------------------------------------------------------
19
20library ieee;
21use ieee.std_logic_1164.all;
22use ieee.numeric_std.all;
23use ieee.std_logic_textio.all;
24use std.textio.all;
25
26use work.slvtypes.all;
27use work.simbus.all;
28
30 port (
31 I_BTN : out slv2 -- c7 buttons
32 );
34
35architecture sim of tb_cmoda7_core is
36
37 signal R_BTN : slv2 := (others=>'0');
38
39 constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
40
41begin
42
43 proc_simbus: process (SB_VAL)
44 begin
45 if SB_VAL'event and to_x01(SB_VAL)='1' then
46 if SB_ADDR = sbaddr_btn then
47 R_BTN <= to_x01(SB_DATA(R_BTN'range));
48 end if;
49 end if;
50 end process proc_simbus;
51
52 I_BTN <= R_BTN;
53
54end sim;
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
std_logic_vector slv
Definition: slvtypes.vhd:31
slv8 := slv( to_unsigned( 17, 8) ) sbaddr_btn
slv2 :=( others => '0') R_BTN