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W11 CPU core and support modules
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arty_dummy.vhd
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-- $Id: arty_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: arty_dummy - syn
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-- Description: arty minimal target (base; serport loopback)
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--
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-- Dependencies: -
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-- To test: tb_arty
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-- Target Devices: generic
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-- Tool versions: viv 2015.4; ghdl 0.33
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2016-03-06 740 1.1 add A_VPWRN/P to baseline config
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-- 2016-01-31 726 1.0 Initial version (cloned from basys3)
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------------------------------------------------------------------------------
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library
ieee
;
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use
ieee.std_logic_1164.
all
;
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use
work.
slvtypes
.
all
;
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entity
arty_dummy
is
-- ARTY dummy (base; loopback)
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-- implements arty_aif
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port
(
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I_CLK100
:
in
slbit
;
-- 100 MHz board clock
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I_RXD
:
in
slbit
;
-- receive data (board view)
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O_TXD
:
out
slbit
;
-- transmit data (board view)
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I_SWI
:
in
slv4
;
-- arty switches
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I_BTN
:
in
slv4
;
-- arty buttons
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O_LED
:
out
slv4
;
-- arty leds
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O_RGBLED0
:
out
slv3
;
-- arty rgb-led 0
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O_RGBLED1
:
out
slv3
;
-- arty rgb-led 1
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O_RGBLED2
:
out
slv3
;
-- arty rgb-led 2
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O_RGBLED3
:
out
slv3
;
-- arty rgb-led 3
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A_VPWRN
:
in
slv4
;
-- arty pwrmon (neg)
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A_VPWRP
:
in
slv4
-- arty pwrmon (pos)
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)
;
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end
arty_dummy
;
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architecture
syn
of
arty_dummy
is
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begin
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O_TXD
<=
I_RXD
;
-- loop back serport
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O_LED
<=
I_SWI
;
-- mirror SWI on LED
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O_RGBLED0
<=
I_BTN
(
2
downto
0
)
;
-- mirror BTN on RGBLED0
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O_RGBLED1
<=
(
others
=
>
'
0
'
)
;
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O_RGBLED2
<=
(
others
=
>
'
0
'
)
;
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O_RGBLED3
<=
(
others
=
>
'
0
'
)
;
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end
syn
;
arty_dummy.syn
Definition:
arty_dummy.vhd:43
arty_dummy
Definition:
arty_dummy.vhd:25
arty_dummy.I_SWI
in I_SWI slv4
Definition:
arty_dummy.vhd:31
arty_dummy.O_TXD
out O_TXD slbit
Definition:
arty_dummy.vhd:30
arty_dummy.I_RXD
in I_RXD slbit
Definition:
arty_dummy.vhd:29
arty_dummy.A_VPWRN
in A_VPWRN slv4
Definition:
arty_dummy.vhd:38
arty_dummy.A_VPWRP
in A_VPWRP slv4
Definition:
arty_dummy.vhd:40
arty_dummy.I_BTN
in I_BTN slv4
Definition:
arty_dummy.vhd:32
arty_dummy.O_RGBLED3
out O_RGBLED3 slv3
Definition:
arty_dummy.vhd:37
arty_dummy.O_RGBLED0
out O_RGBLED0 slv3
Definition:
arty_dummy.vhd:34
arty_dummy.I_CLK100
in I_CLK100 slbit
Definition:
arty_dummy.vhd:28
arty_dummy.O_RGBLED2
out O_RGBLED2 slv3
Definition:
arty_dummy.vhd:36
arty_dummy.O_RGBLED1
out O_RGBLED1 slv3
Definition:
arty_dummy.vhd:35
arty_dummy.O_LED
out O_LED slv4
Definition:
arty_dummy.vhd:33
slvtypes
Definition:
slvtypes.vhd:28
slvtypes.slv4
std_logic_vector( 3 downto 0) slv4
Definition:
slvtypes.vhd:36
slvtypes.slv3
std_logic_vector( 2 downto 0) slv3
Definition:
slvtypes.vhd:35
slvtypes.slbit
std_logic slbit
Definition:
slvtypes.vhd:30
bplib
arty
tb
arty_dummy.vhd
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