fifo_1c_dram Entity Reference

Inheritance diagram for fifo_1c_dram:

Collaboration diagram for fifo_1c_dram:

Entities
syn	architecture

Libraries
ieee

Use Clauses
std_logic_1164
slvtypes	Package <slvtypes>
memlib	Package <memlib>

Generics
AWIDTH	positive := 7
DWIDTH	positive := 16

Ports
CLK	in	slbit
RESET	in	slbit
DI	in	slv ( DWIDTH - 1 downto 0 )
ENA	in	slbit
BUSY	out	slbit
DO	out	slv ( DWIDTH - 1 downto 0 )
VAL	out	slbit
HOLD	in	slbit
SIZE	out	slv ( AWIDTH downto 0 )

Detailed Description

Definition at line 34 of file fifo_1c_dram.vhd.

Member Data Documentation

AWIDTH

AWIDTH positive := 7

Generic

Definition at line 36 of file fifo_1c_dram.vhd.

DWIDTH

DWIDTH positive := 16

Generic

Definition at line 37 of file fifo_1c_dram.vhd.

CLK

CLK in slbit

Port

Definition at line 39 of file fifo_1c_dram.vhd.

RESET

RESET in slbit

Port

Definition at line 40 of file fifo_1c_dram.vhd.

DI

DI in slv ( DWIDTH - 1 downto 0 )

Port

Definition at line 41 of file fifo_1c_dram.vhd.

ENA

ENA in slbit

Port

Definition at line 42 of file fifo_1c_dram.vhd.

BUSY

BUSY out slbit

Port

Definition at line 43 of file fifo_1c_dram.vhd.

DO

DO out slv ( DWIDTH - 1 downto 0 )

Port

Definition at line 44 of file fifo_1c_dram.vhd.

VAL

VAL out slbit

Port

Definition at line 45 of file fifo_1c_dram.vhd.

HOLD

HOLD in slbit

Port

Definition at line 46 of file fifo_1c_dram.vhd.

SIZE

SIZE out slv ( AWIDTH downto 0 )

Port

Definition at line 48 of file fifo_1c_dram.vhd.

ieee

ieee

Library

Definition at line 28 of file fifo_1c_dram.vhd.

std_logic_1164

std_logic_1164

use clause

Definition at line 29 of file fifo_1c_dram.vhd.

slvtypes

slvtypes

use clause

Definition at line 31 of file fifo_1c_dram.vhd.

memlib

memlib

use clause

Definition at line 32 of file fifo_1c_dram.vhd.

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The documentation for this design unit was generated from the following file:

• vlib/memlib/fifo_1c_dram.vhd