syn Architecture Reference

Architecture >> syn

Signals
WE	slbit := ' 0 '
RE	slbit := ' 0 '
SIZE_L	slv ( AWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
EMPTY	slbit := ' 0 '
FULL	slbit := ' 0 '

Instantiations
fifo	fifo_1c_dram_raw <Entity fifo_1c_dram_raw>

Detailed Description

Definition at line 52 of file fifo_1c_dram.vhd.

Member Data Documentation

WE

WE slbit := ' 0 '

Signal

Definition at line 54 of file fifo_1c_dram.vhd.

RE

RE slbit := ' 0 '

Signal

Definition at line 55 of file fifo_1c_dram.vhd.

SIZE_L

SIZE_L slv ( AWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Definition at line 56 of file fifo_1c_dram.vhd.

EMPTY

EMPTY slbit := ' 0 '

Signal

Definition at line 57 of file fifo_1c_dram.vhd.

FULL

FULL slbit := ' 0 '

Signal

Definition at line 58 of file fifo_1c_dram.vhd.

fifo

fifo fifo_1c_dram_raw

Instantiation

Definition at line 76 of file fifo_1c_dram.vhd.

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The documentation for this design unit was generated from the following file:

• vlib/memlib/fifo_1c_dram.vhd