w11 - vhd 0.794
W11 CPU core and support modules
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fifo_1c_dram.vhd
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1-- $Id: fifo_1c_dram.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: fifo_1c_dram - syn
7-- Description: FIFO, single clock domain, distributed RAM based, with
8-- enable/busy/valid/hold interface.
9--
10-- Dependencies: fifo_1c_dram_raw
11--
12-- Test bench: tb/tb_fifo_1c_dram
13-- Target Devices: generic Spartan, Virtex
14-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31
15-- Revision History:
16-- Date Rev Version Comment
17-- 2007-06-06 49 1.0 Initial version
18--
19-- Some synthesis results:
20-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
21-- AWIDTH DWIDTH LUT.l LUT.m Flop clock(xst est.)
22-- 4 16 31 32 22 153MHz ( 16 words)
23-- 5 16 49 64 23 120MHz ( 32 words)
24-- 6 16 70 128 23 120MHz ( 64 words)
25-- 7 16 111 256 30 120MHz (128 words)
26------------------------------------------------------------------------------
27
28library ieee;
29use ieee.std_logic_1164.all;
30
31use work.slvtypes.all;
32use work.memlib.all;
33
34entity fifo_1c_dram is -- fifo, 1 clock, dram based
35 generic (
36 AWIDTH : positive := 7; -- address width (sets size)
37 DWIDTH : positive := 16); -- data width
38 port (
39 CLK : in slbit; -- clock
40 RESET : in slbit; -- reset
41 DI : in slv(DWIDTH-1 downto 0); -- input data
42 ENA : in slbit; -- write enable
43 BUSY : out slbit; -- write port hold
44 DO : out slv(DWIDTH-1 downto 0); -- output data
45 VAL : out slbit; -- read valid
46 HOLD : in slbit; -- read hold
47 SIZE : out slv(AWIDTH downto 0) -- number of used slots
48 );
49end fifo_1c_dram;
50
51
52architecture syn of fifo_1c_dram is
53
54 signal WE : slbit := '0';
55 signal RE : slbit := '0';
56 signal SIZE_L : slv(AWIDTH-1 downto 0) := (others=>'0');
57 signal EMPTY : slbit := '0';
58 signal FULL : slbit := '0';
59
60begin
61
62 FIFO : fifo_1c_dram_raw
63 generic map (
64 AWIDTH => AWIDTH,
65 DWIDTH => DWIDTH)
66 port map (
67 CLK => CLK,
68 RESET => RESET,
69 WE => WE,
70 RE => RE,
71 DI => DI,
72 DO => DO,
73 SIZE => SIZE_L,
74 EMPTY => EMPTY,
75 FULL => FULL
76 );
77
78 WE <= ENA and (not FULL);
79 RE <= (not EMPTY) and (not HOLD);
80
81 BUSY <= FULL;
82 VAL <= not EMPTY;
83 SIZE <= FULL & SIZE_L;
84
85end syn;
slbit := '0' RE
slv( AWIDTH- 1 downto 0) :=( others => '0') SIZE_L
slbit := '0' FULL
slbit := '0' EMPTY
slbit := '0' WE
out DO slv( DWIDTH- 1 downto 0)
AWIDTH positive := 4
in DI slv( DWIDTH- 1 downto 0)
out SIZE slv( AWIDTH- 1 downto 0)
DWIDTH positive := 16
in RESET slbit
in ENA slbit
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)
out BUSY slbit
in HOLD slbit
in CLK slbit
AWIDTH positive := 7
out SIZE slv( AWIDTH downto 0)
DWIDTH positive := 16
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector slv
Definition: slvtypes.vhd:31