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Generics | Libraries | Ports | Use Clauses
mig_7series_v4_2_ddr_phy_top Entity Reference

Entities

arch_ddr_phy_top  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
numeric_std 

Generics

TCQ  integer := 100
DDR3_VDD_OP_VOLT  string := " 135 "
AL  string := " 0 "
BANK_WIDTH  integer := 3
BURST_MODE  string := " 8 "
BURST_TYPE  string := " SEQ "
CA_MIRROR  string := " OFF "
CK_WIDTH  integer := 1
CL  integer := 5
COL_WIDTH  integer := 12
CS_WIDTH  integer := 1
CKE_WIDTH  integer := 1
CWL  integer := 5
DM_WIDTH  integer := 8
DQ_WIDTH  integer := 64
DQS_CNT_WIDTH  integer := 3
DQS_WIDTH  integer := 8
DRAM_TYPE  string := " DDR3 "
DRAM_WIDTH  integer := 8
MASTER_PHY_CTL  integer := 0
LP_DDR_CK_WIDTH  integer := 2
PHYCTL_CMD_FIFO  string := " FALSE "
DATA_CTL_B0  std_logic_vector ( 3 downto 0 ) := X " c "
DATA_CTL_B1  std_logic_vector ( 3 downto 0 ) := X " f "
DATA_CTL_B2  std_logic_vector ( 3 downto 0 ) := X " f "
DATA_CTL_B3  std_logic_vector ( 3 downto 0 ) := X " f "
DATA_CTL_B4  std_logic_vector ( 3 downto 0 ) := X " f "
BYTE_LANES_B0  std_logic_vector ( 3 downto 0 ) := " 1111 "
BYTE_LANES_B1  std_logic_vector ( 3 downto 0 ) := " 0000 "
BYTE_LANES_B2  std_logic_vector ( 3 downto 0 ) := " 0000 "
BYTE_LANES_B3  std_logic_vector ( 3 downto 0 ) := " 0000 "
BYTE_LANES_B4  std_logic_vector ( 3 downto 0 ) := " 0000 "
PHY_0_BITLANES  std_logic_vector ( 47 downto 0 ) := X " 000000000000 "
PHY_1_BITLANES  std_logic_vector ( 47 downto 0 ) := X " 000000000000 "
PHY_2_BITLANES  std_logic_vector ( 47 downto 0 ) := X " 000000000000 "
CK_BYTE_MAP  std_logic_vector ( 143 downto 0 ) := X " 000000000000000000000000000000000000 "
ADDR_MAP  std_logic_vector ( 191 downto 0 ) := X " 000000000000000000000000000000000000000000000000 "
BANK_MAP  std_logic_vector ( 35 downto 0 ) := X " 000000000 "
CAS_MAP  std_logic_vector ( 11 downto 0 ) := X " 000 "
CKE_ODT_BYTE_MAP  std_logic_vector ( 7 downto 0 ) := X " 00 "
CKE_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
ODT_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
CKE_ODT_AUX  string := " FALSE "
CS_MAP  std_logic_vector ( 119 downto 0 ) := X " 000000000000000000000000000000 "
PARITY_MAP  std_logic_vector ( 11 downto 0 ) := X " 000 "
RAS_MAP  std_logic_vector ( 11 downto 0 ) := X " 000 "
WE_MAP  std_logic_vector ( 11 downto 0 ) := X " 000 "
DQS_BYTE_MAP  std_logic_vector ( 143 downto 0 ) := X " 000000000000000000000000000000000000 "
DATA0_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA1_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA2_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA3_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA4_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA5_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA6_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA7_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA8_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA9_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA10_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA11_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA12_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA13_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA14_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA15_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA16_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA17_MAP  std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
MASK0_MAP  std_logic_vector ( 107 downto 0 ) := X " 000000000000000000000000000 "
MASK1_MAP  std_logic_vector ( 107 downto 0 ) := X " 000000000000000000000000000 "
PRE_REV3ES  string := " OFF "
nCK_PER_CLK  integer := 2
nCS_PER_RANK  integer := 1
ADDR_CMD_MODE  string := " 1T "
BANK_TYPE  string := " HP_IO "
DATA_IO_PRIM_TYPE  string := " DEFAULT "
DATA_IO_IDLE_PWRDWN  string := " ON "
IODELAY_GRP  string := " IODELAY_MIG "
FPGA_SPEED_GRADE  integer := 1
IBUF_LPWR_MODE  string := " OFF "
OUTPUT_DRV  string := " HIGH "
REG_CTRL  string := " OFF "
RTT_NOM  string := " 60 "
RTT_WR  string := " 120 "
tCK  integer := 2500
tRFC  integer := 110000
tREFI  integer := 7800000
DDR2_DQSN_ENABLE  string := " YES "
WRLVL  string := " OFF "
DEBUG_PORT  string := " OFF "
RANKS  integer := 4
ODT_WIDTH  integer := 1
ROW_WIDTH  integer := 16
SLOT_1_CONFIG  std_logic_vector ( 7 downto 0 ) := " 00000000 "
CALIB_ROW_ADD  std_logic_vector ( 15 downto 0 ) := X " 0000 "
CALIB_COL_ADD  std_logic_vector ( 11 downto 0 ) := X " 000 "
CALIB_BA_ADD  std_logic_vector ( 2 downto 0 ) := " 000 "
SIM_BYPASS_INIT_CAL  string := " OFF "
REFCLK_FREQ  real := 200 . 0
USE_CS_PORT  integer := 1
USE_DM_PORT  integer := 1
USE_ODT_PORT  integer := 1
RD_PATH_REG  integer := 0
IDELAY_ADJ  string := " ON "
FINE_PER_BIT  string := " ON "
CENTER_COMP_MODE  string := " ON "
PI_VAL_ADJ  string := " ON "
TAPSPERKCLK  integer := 56
SKIP_CALIB  string := " FALSE "
POC_USE_METASTABLE_SAMP  string := " FALSE "
FPGA_VOLT_TYPE  string := " N "

Ports

clk   in   std_logic
clk_div2   in   std_logic
rst_div2   in   std_logic
clk_ref   in   std_logic
freq_refclk   in   std_logic
mem_refclk   in   std_logic
pll_lock   in   std_logic
sync_pulse   in   std_logic
mmcm_ps_clk   in   std_logic
poc_sample_pd   in   std_logic
error   in   std_logic
rst_tg_mc   out   std_logic
device_temp   in   std_logic_vector ( 11 downto 0 )
tempmon_sample_en   in   std_logic
dbg_sel_pi_incdec   in   std_logic
dbg_sel_po_incdec   in   std_logic
dbg_byte_sel   in   std_logic_vector ( DQS_CNT_WIDTH downto 0 )
dbg_pi_f_inc   in   std_logic
dbg_pi_f_dec   in   std_logic
dbg_po_f_inc   in   std_logic
dbg_po_f_stg23_sel   in   std_logic
dbg_po_f_dec   in   std_logic
dbg_idel_down_all   in   std_logic
dbg_idel_down_cpt   in   std_logic
dbg_idel_up_all   in   std_logic
dbg_idel_up_cpt   in   std_logic
dbg_sel_all_idel_cpt   in   std_logic
dbg_sel_idel_cpt   in   std_logic_vector ( DQS_CNT_WIDTH - 1 downto 0 )
rst   in   std_logic
iddr_rst   in   std_logic
slot_0_present   in   std_logic_vector ( 7 downto 0 )
slot_1_present   in   std_logic_vector ( 7 downto 0 )
mc_ras_n   in   std_logic_vector ( nCK_PER_CLK - 1 downto 0 )
mc_cas_n   in   std_logic_vector ( nCK_PER_CLK - 1 downto 0 )
mc_we_n   in   std_logic_vector ( nCK_PER_CLK - 1 downto 0 )
mc_address   in   std_logic_vector ( nCK_PER_CLK * ROW_WIDTH - 1 downto 0 )
mc_bank   in   std_logic_vector ( nCK_PER_CLK * BANK_WIDTH - 1 downto 0 )
mc_cs_n   in   std_logic_vector ( CS_WIDTH * nCS_PER_RANK * nCK_PER_CLK - 1 downto 0 )
mc_reset_n   in   std_logic
mc_odt   in   std_logic_vector ( 1 downto 0 )
mc_cke   in   std_logic_vector ( nCK_PER_CLK - 1 downto 0 )
mc_aux_out0   in   std_logic_vector ( 3 downto 0 )
mc_aux_out1   in   std_logic_vector ( 3 downto 0 )
mc_cmd_wren   in   std_logic
mc_ctl_wren   in   std_logic
mc_cmd   in   std_logic_vector ( 2 downto 0 )
mc_cas_slot   in   std_logic_vector ( 1 downto 0 )
mc_data_offset   in   std_logic_vector ( 5 downto 0 )
mc_data_offset_1   in   std_logic_vector ( 5 downto 0 )
mc_data_offset_2   in   std_logic_vector ( 5 downto 0 )
mc_rank_cnt   in   std_logic_vector ( 1 downto 0 )
mc_wrdata_en   in   std_logic
mc_wrdata   in   std_logic_vector ( 2 * nCK_PER_CLK * DQ_WIDTH - 1 downto 0 )
mc_wrdata_mask   in   std_logic_vector ( ( 2 * nCK_PER_CLK * ( DQ_WIDTH / 8 ) ) - 1 downto 0 )
idle   in   std_logic
ddr_addr   out   std_logic_vector ( ROW_WIDTH - 1 downto 0 )
ddr_ba   out   std_logic_vector ( BANK_WIDTH - 1 downto 0 )
ddr_cas_n   out   std_logic
ddr_ck_n   out   std_logic_vector ( CK_WIDTH - 1 downto 0 )
ddr_ck   out   std_logic_vector ( CK_WIDTH - 1 downto 0 )
ddr_cke   out   std_logic_vector ( CKE_WIDTH - 1 downto 0 )
ddr_cs_n   out   std_logic_vector ( ( CS_WIDTH * nCS_PER_RANK ) - 1 downto 0 )
ddr_dm   out   std_logic_vector ( DM_WIDTH - 1 downto 0 )
ddr_odt   out   std_logic_vector ( ODT_WIDTH - 1 downto 0 )
ddr_ras_n   out   std_logic
ddr_reset_n   out   std_logic
ddr_parity   out   std_logic
ddr_we_n   out   std_logic
ddr_dq   inout   std_logic_vector ( DQ_WIDTH - 1 downto 0 )
ddr_dqs_n   inout   std_logic_vector ( DQS_WIDTH - 1 downto 0 )
ddr_dqs   inout   std_logic_vector ( DQS_WIDTH - 1 downto 0 )
psen   out   std_logic
psincdec   out   std_logic
psdone   in   std_logic
calib_tap_req   out   std_logic
calib_tap_load   in   std_logic
calib_tap_addr   in   std_logic_vector ( 6 downto 0 )
calib_tap_val   in   std_logic_vector ( 7 downto 0 )
calib_tap_load_done   in   std_logic
dbg_calib_top   out   std_logic_vector ( 255 downto 0 )
dbg_cpt_first_edge_cnt   out   std_logic_vector ( 6 * DQS_WIDTH * RANKS - 1 downto 0 )
dbg_cpt_second_edge_cnt   out   std_logic_vector ( 6 * DQS_WIDTH * RANKS - 1 downto 0 )
dbg_cpt_tap_cnt   out   std_logic_vector ( 6 * DQS_WIDTH * RANKS - 1 downto 0 )
dbg_dq_idelay_tap_cnt   out   std_logic_vector ( 5 * DQS_WIDTH * RANKS - 1 downto 0 )
dbg_phy_rdlvl   out   std_logic_vector ( 255 downto 0 )
dbg_phy_wrcal   out   std_logic_vector ( 99 downto 0 )
dbg_final_po_fine_tap_cnt   out   std_logic_vector ( 6 * DQS_WIDTH - 1 downto 0 )
dbg_final_po_coarse_tap_cnt   out   std_logic_vector ( 3 * DQS_WIDTH - 1 downto 0 )
dbg_rd_data_edge_detect   out   std_logic_vector ( DQS_WIDTH - 1 downto 0 )
dbg_rddata   out   std_logic_vector ( 2 * nCK_PER_CLK * DQ_WIDTH - 1 downto 0 )
dbg_rddata_valid   out   std_logic
dbg_rdlvl_done   out   std_logic_vector ( 1 downto 0 )
dbg_rdlvl_err   out   std_logic_vector ( 1 downto 0 )
dbg_rdlvl_start   out   std_logic_vector ( 1 downto 0 )
dbg_tap_cnt_during_wrlvl   out   std_logic_vector ( 5 downto 0 )
dbg_wl_edge_detect_valid   out   std_logic
dbg_wrlvl_done   out   std_logic
dbg_wrlvl_err   out   std_logic
dbg_wrlvl_start   out   std_logic
dbg_wrlvl_fine_tap_cnt   out   std_logic_vector ( 6 * DQS_WIDTH - 1 downto 0 )
dbg_wrlvl_coarse_tap_cnt   out   std_logic_vector ( 3 * DQS_WIDTH - 1 downto 0 )
dbg_phy_wrlvl   out   std_logic_vector ( 255 downto 0 )
dbg_pi_phaselock_start   out   std_logic
dbg_pi_phaselocked_done   out   std_logic
dbg_pi_phaselock_err   out   std_logic
dbg_pi_phase_locked_phy4lanes   out   std_logic_vector ( 11 downto 0 )
dbg_pi_dqsfound_start   out   std_logic
dbg_pi_dqsfound_done   out   std_logic
dbg_pi_dqsfound_err   out   std_logic
dbg_pi_dqs_found_lanes_phy4lanes   out   std_logic_vector ( 11 downto 0 )
dbg_wrcal_start   out   std_logic
dbg_wrcal_done   out   std_logic
dbg_wrcal_err   out   std_logic
dbg_poc   out   std_logic_vector ( 1023 downto 0 )
phy_mc_ctl_full   out   std_logic
phy_mc_cmd_full   out   std_logic
phy_mc_data_full   out   std_logic
init_calib_complete   out   std_logic
init_wrcal_complete   out   std_logic
calib_rd_data_offset_0   out   std_logic_vector ( 6 * RANKS - 1 downto 0 )
calib_rd_data_offset_1   out   std_logic_vector ( 6 * RANKS - 1 downto 0 )
calib_rd_data_offset_2   out   std_logic_vector ( 6 * RANKS - 1 downto 0 )
phy_rddata_valid   out   std_logic
phy_rd_data   out   std_logic_vector ( 2 * nCK_PER_CLK * DQ_WIDTH - 1 downto 0 )
ref_dll_lock   out   std_logic
rst_phaser_ref   in   std_logic
dbg_rd_data_offset   out   std_logic_vector ( 6 * RANKS - 1 downto 0 )
dbg_phy_init   out   std_logic_vector ( 255 downto 0 )
dbg_prbs_rdlvl   out   std_logic_vector ( 255 downto 0 )
dbg_dqs_found_cal   out   std_logic_vector ( 255 downto 0 )
dbg_pi_counter_read_val   out   std_logic_vector ( 5 downto 0 )
dbg_po_counter_read_val   out   std_logic_vector ( 8 downto 0 )
dbg_oclkdelay_calib_start   out   std_logic
dbg_oclkdelay_calib_done   out   std_logic
dbg_phy_oclkdelay_cal   out   std_logic_vector ( 255 downto 0 )
dbg_oclkdelay_rd_data   out   std_logic_vector ( DRAM_WIDTH * 16 - 1 downto 0 )
prbs_final_dqs_tap_cnt_r   out   std_logic_vector ( 6 * DQS_WIDTH * RANKS - 1 downto 0 )
dbg_prbs_first_edge_taps   out   std_logic_vector ( 6 * DQS_WIDTH * RANKS - 1 downto 0 )
dbg_prbs_second_edge_taps   out   std_logic_vector ( 6 * DQS_WIDTH * RANKS - 1 downto 0 )

Detailed Description

Definition at line 73 of file mig_7series_v4_2_ddr_phy_top.vhd.

Member Data Documentation

◆ TCQ

TCQ integer := 100
Generic

Definition at line 76 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DDR3_VDD_OP_VOLT

DDR3_VDD_OP_VOLT string := " 135 "
Generic

Definition at line 77 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ AL

AL string := " 0 "
Generic

Definition at line 78 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ BANK_WIDTH

BANK_WIDTH integer := 3
Generic

Definition at line 79 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ BURST_MODE

BURST_MODE string := " 8 "
Generic

Definition at line 80 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ BURST_TYPE

BURST_TYPE string := " SEQ "
Generic

Definition at line 81 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CA_MIRROR

CA_MIRROR string := " OFF "
Generic

Definition at line 82 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CK_WIDTH

CK_WIDTH integer := 1
Generic

Definition at line 83 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CL

CL integer := 5
Generic

Definition at line 84 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ COL_WIDTH

COL_WIDTH integer := 12
Generic

Definition at line 85 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CS_WIDTH

CS_WIDTH integer := 1
Generic

Definition at line 86 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CKE_WIDTH

CKE_WIDTH integer := 1
Generic

Definition at line 87 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CWL

CWL integer := 5
Generic

Definition at line 88 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DM_WIDTH

DM_WIDTH integer := 8
Generic

Definition at line 89 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DQ_WIDTH

DQ_WIDTH integer := 64
Generic

Definition at line 90 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DQS_CNT_WIDTH

DQS_CNT_WIDTH integer := 3
Generic

Definition at line 91 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DQS_WIDTH

DQS_WIDTH integer := 8
Generic

Definition at line 92 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DRAM_TYPE

DRAM_TYPE string := " DDR3 "
Generic

Definition at line 93 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DRAM_WIDTH

DRAM_WIDTH integer := 8
Generic

Definition at line 94 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ MASTER_PHY_CTL

MASTER_PHY_CTL integer := 0
Generic

Definition at line 95 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ LP_DDR_CK_WIDTH

LP_DDR_CK_WIDTH integer := 2
Generic

Definition at line 96 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PHYCTL_CMD_FIFO

PHYCTL_CMD_FIFO string := " FALSE "
Generic

Definition at line 98 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DATA_CTL_B0

DATA_CTL_B0 std_logic_vector ( 3 downto 0 ) := X " c "
Generic

Definition at line 101 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DATA_CTL_B1

DATA_CTL_B1 std_logic_vector ( 3 downto 0 ) := X " f "
Generic

Definition at line 102 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DATA_CTL_B2

DATA_CTL_B2 std_logic_vector ( 3 downto 0 ) := X " f "
Generic

Definition at line 103 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DATA_CTL_B3

DATA_CTL_B3 std_logic_vector ( 3 downto 0 ) := X " f "
Generic

Definition at line 104 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DATA_CTL_B4

DATA_CTL_B4 std_logic_vector ( 3 downto 0 ) := X " f "
Generic

Definition at line 105 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ BYTE_LANES_B0

BYTE_LANES_B0 std_logic_vector ( 3 downto 0 ) := " 1111 "
Generic

Definition at line 108 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ BYTE_LANES_B1

BYTE_LANES_B1 std_logic_vector ( 3 downto 0 ) := " 0000 "
Generic

Definition at line 109 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ BYTE_LANES_B2

BYTE_LANES_B2 std_logic_vector ( 3 downto 0 ) := " 0000 "
Generic

Definition at line 110 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ BYTE_LANES_B3

BYTE_LANES_B3 std_logic_vector ( 3 downto 0 ) := " 0000 "
Generic

Definition at line 111 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ BYTE_LANES_B4

BYTE_LANES_B4 std_logic_vector ( 3 downto 0 ) := " 0000 "
Generic

Definition at line 112 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PHY_0_BITLANES

PHY_0_BITLANES std_logic_vector ( 47 downto 0 ) := X " 000000000000 "
Generic

Definition at line 115 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PHY_1_BITLANES

PHY_1_BITLANES std_logic_vector ( 47 downto 0 ) := X " 000000000000 "
Generic

Definition at line 116 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PHY_2_BITLANES

PHY_2_BITLANES std_logic_vector ( 47 downto 0 ) := X " 000000000000 "
Generic

Definition at line 117 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CK_BYTE_MAP

CK_BYTE_MAP std_logic_vector ( 143 downto 0 ) := X " 000000000000000000000000000000000000 "
Generic

Definition at line 120 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ADDR_MAP

ADDR_MAP std_logic_vector ( 191 downto 0 ) := X " 000000000000000000000000000000000000000000000000 "
Generic

Definition at line 121 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ BANK_MAP

BANK_MAP std_logic_vector ( 35 downto 0 ) := X " 000000000 "
Generic

Definition at line 122 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CAS_MAP

CAS_MAP std_logic_vector ( 11 downto 0 ) := X " 000 "
Generic

Definition at line 123 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CKE_ODT_BYTE_MAP

CKE_ODT_BYTE_MAP std_logic_vector ( 7 downto 0 ) := X " 00 "
Generic

Definition at line 124 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CKE_MAP

CKE_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 125 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ODT_MAP

ODT_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 126 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CKE_ODT_AUX

CKE_ODT_AUX string := " FALSE "
Generic

Definition at line 127 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CS_MAP

CS_MAP std_logic_vector ( 119 downto 0 ) := X " 000000000000000000000000000000 "
Generic

Definition at line 128 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PARITY_MAP

PARITY_MAP std_logic_vector ( 11 downto 0 ) := X " 000 "
Generic

Definition at line 129 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ RAS_MAP

RAS_MAP std_logic_vector ( 11 downto 0 ) := X " 000 "
Generic

Definition at line 130 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ WE_MAP

WE_MAP std_logic_vector ( 11 downto 0 ) := X " 000 "
Generic

Definition at line 131 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DQS_BYTE_MAP

DQS_BYTE_MAP std_logic_vector ( 143 downto 0 ) := X " 000000000000000000000000000000000000 "
Generic

Definition at line 133 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DATA0_MAP

DATA0_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 134 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DATA1_MAP

DATA1_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 135 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DATA2_MAP

DATA2_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 136 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DATA3_MAP

DATA3_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 137 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DATA4_MAP

DATA4_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 138 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DATA5_MAP

DATA5_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 139 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DATA6_MAP

DATA6_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 140 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DATA7_MAP

DATA7_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 141 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DATA8_MAP

DATA8_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 142 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DATA9_MAP

DATA9_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 143 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DATA10_MAP

DATA10_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 144 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DATA11_MAP

DATA11_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 145 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DATA12_MAP

DATA12_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 146 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DATA13_MAP

DATA13_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 147 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DATA14_MAP

DATA14_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 148 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DATA15_MAP

DATA15_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 149 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DATA16_MAP

DATA16_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 150 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DATA17_MAP

DATA17_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
Generic

Definition at line 151 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ MASK0_MAP

MASK0_MAP std_logic_vector ( 107 downto 0 ) := X " 000000000000000000000000000 "
Generic

Definition at line 152 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ MASK1_MAP

MASK1_MAP std_logic_vector ( 107 downto 0 ) := X " 000000000000000000000000000 "
Generic

Definition at line 153 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PRE_REV3ES

PRE_REV3ES string := " OFF "
Generic

Definition at line 158 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ nCK_PER_CLK

nCK_PER_CLK integer := 2
Generic

Definition at line 159 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ nCS_PER_RANK

nCS_PER_RANK integer := 1
Generic

Definition at line 160 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ADDR_CMD_MODE

ADDR_CMD_MODE string := " 1T "
Generic

Definition at line 161 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ BANK_TYPE

BANK_TYPE string := " HP_IO "
Generic

Definition at line 162 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DATA_IO_PRIM_TYPE

DATA_IO_PRIM_TYPE string := " DEFAULT "
Generic

Definition at line 163 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DATA_IO_IDLE_PWRDWN

DATA_IO_IDLE_PWRDWN string := " ON "
Generic

Definition at line 164 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ IODELAY_GRP

IODELAY_GRP string := " IODELAY_MIG "
Generic

Definition at line 165 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ FPGA_SPEED_GRADE

FPGA_SPEED_GRADE integer := 1
Generic

Definition at line 166 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ IBUF_LPWR_MODE

IBUF_LPWR_MODE string := " OFF "
Generic

Definition at line 167 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ OUTPUT_DRV

OUTPUT_DRV string := " HIGH "
Generic

Definition at line 168 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ REG_CTRL

REG_CTRL string := " OFF "
Generic

Definition at line 169 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ RTT_NOM

RTT_NOM string := " 60 "
Generic

Definition at line 170 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ RTT_WR

RTT_WR string := " 120 "
Generic

Definition at line 171 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ tCK

tCK integer := 2500
Generic

Definition at line 172 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ tRFC

tRFC integer := 110000
Generic

Definition at line 173 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ tREFI

tREFI integer := 7800000
Generic

Definition at line 174 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DDR2_DQSN_ENABLE

DDR2_DQSN_ENABLE string := " YES "
Generic

Definition at line 175 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ WRLVL

WRLVL string := " OFF "
Generic

Definition at line 176 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ DEBUG_PORT

DEBUG_PORT string := " OFF "
Generic

Definition at line 177 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ RANKS

RANKS integer := 4
Generic

Definition at line 178 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ODT_WIDTH

ODT_WIDTH integer := 1
Generic

Definition at line 179 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ROW_WIDTH

ROW_WIDTH integer := 16
Generic

Definition at line 180 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ SLOT_1_CONFIG

SLOT_1_CONFIG std_logic_vector ( 7 downto 0 ) := " 00000000 "
Generic

Definition at line 181 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CALIB_ROW_ADD

CALIB_ROW_ADD std_logic_vector ( 15 downto 0 ) := X " 0000 "
Generic

Definition at line 184 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CALIB_COL_ADD

CALIB_COL_ADD std_logic_vector ( 11 downto 0 ) := X " 000 "
Generic

Definition at line 185 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CALIB_BA_ADD

CALIB_BA_ADD std_logic_vector ( 2 downto 0 ) := " 000 "
Generic

Definition at line 186 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ SIM_BYPASS_INIT_CAL

SIM_BYPASS_INIT_CAL string := " OFF "
Generic

Definition at line 188 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ REFCLK_FREQ

REFCLK_FREQ real := 200 . 0
Generic

Definition at line 196 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ USE_CS_PORT

USE_CS_PORT integer := 1
Generic

Definition at line 197 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ USE_DM_PORT

USE_DM_PORT integer := 1
Generic

Definition at line 198 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ USE_ODT_PORT

USE_ODT_PORT integer := 1
Generic

Definition at line 199 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ RD_PATH_REG

RD_PATH_REG integer := 0
Generic

Definition at line 200 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ IDELAY_ADJ

IDELAY_ADJ string := " ON "
Generic

Definition at line 203 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ FINE_PER_BIT

FINE_PER_BIT string := " ON "
Generic

Definition at line 204 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CENTER_COMP_MODE

CENTER_COMP_MODE string := " ON "
Generic

Definition at line 205 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PI_VAL_ADJ

PI_VAL_ADJ string := " ON "
Generic

Definition at line 206 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ TAPSPERKCLK

TAPSPERKCLK integer := 56
Generic

Definition at line 207 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ SKIP_CALIB

SKIP_CALIB string := " FALSE "
Generic

Definition at line 208 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ POC_USE_METASTABLE_SAMP

POC_USE_METASTABLE_SAMP string := " FALSE "
Generic

Definition at line 209 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ FPGA_VOLT_TYPE

FPGA_VOLT_TYPE string := " N "
Generic

Definition at line 211 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ clk

clk in std_logic
Port

Definition at line 213 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ clk_div2

clk_div2 in std_logic
Port

Definition at line 215 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ rst_div2

rst_div2 in std_logic
Port

Definition at line 216 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ clk_ref

clk_ref in std_logic
Port

Definition at line 217 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ freq_refclk

freq_refclk in std_logic
Port

Definition at line 219 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mem_refclk

mem_refclk in std_logic
Port

Definition at line 220 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pll_lock

pll_lock in std_logic
Port

Definition at line 221 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ sync_pulse

sync_pulse in std_logic
Port

Definition at line 222 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mmcm_ps_clk

mmcm_ps_clk in std_logic
Port

Definition at line 224 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ poc_sample_pd

poc_sample_pd in std_logic
Port

Definition at line 225 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ error

error in std_logic
Port

Definition at line 226 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ rst_tg_mc

rst_tg_mc out std_logic
Port

Definition at line 227 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ device_temp

device_temp in std_logic_vector ( 11 downto 0 )
Port

Definition at line 229 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ tempmon_sample_en

tempmon_sample_en in std_logic
Port

Definition at line 230 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_sel_pi_incdec

dbg_sel_pi_incdec in std_logic
Port

Definition at line 232 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_sel_po_incdec

dbg_sel_po_incdec in std_logic
Port

Definition at line 233 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_byte_sel

dbg_byte_sel in std_logic_vector ( DQS_CNT_WIDTH downto 0 )
Port

Definition at line 234 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_pi_f_inc

dbg_pi_f_inc in std_logic
Port

Definition at line 235 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_pi_f_dec

dbg_pi_f_dec in std_logic
Port

Definition at line 236 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_po_f_inc

dbg_po_f_inc in std_logic
Port

Definition at line 237 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_po_f_stg23_sel

dbg_po_f_stg23_sel in std_logic
Port

Definition at line 238 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_po_f_dec

dbg_po_f_dec in std_logic
Port

Definition at line 239 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_idel_down_all

dbg_idel_down_all in std_logic
Port

Definition at line 240 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_idel_down_cpt

dbg_idel_down_cpt in std_logic
Port

Definition at line 241 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_idel_up_all

dbg_idel_up_all in std_logic
Port

Definition at line 242 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_idel_up_cpt

dbg_idel_up_cpt in std_logic
Port

Definition at line 243 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_sel_all_idel_cpt

dbg_sel_all_idel_cpt in std_logic
Port

Definition at line 244 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_sel_idel_cpt

dbg_sel_idel_cpt in std_logic_vector ( DQS_CNT_WIDTH - 1 downto 0 )
Port

Definition at line 245 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ rst

rst in std_logic
Port

Definition at line 246 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ iddr_rst

iddr_rst in std_logic
Port

Definition at line 247 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ slot_0_present

slot_0_present in std_logic_vector ( 7 downto 0 )
Port

Definition at line 248 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ slot_1_present

slot_1_present in std_logic_vector ( 7 downto 0 )
Port

Definition at line 249 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mc_ras_n

mc_ras_n in std_logic_vector ( nCK_PER_CLK - 1 downto 0 )
Port

Definition at line 251 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mc_cas_n

mc_cas_n in std_logic_vector ( nCK_PER_CLK - 1 downto 0 )
Port

Definition at line 252 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mc_we_n

mc_we_n in std_logic_vector ( nCK_PER_CLK - 1 downto 0 )
Port

Definition at line 253 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mc_address

mc_address in std_logic_vector ( nCK_PER_CLK * ROW_WIDTH - 1 downto 0 )
Port

Definition at line 254 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mc_bank

mc_bank in std_logic_vector ( nCK_PER_CLK * BANK_WIDTH - 1 downto 0 )
Port

Definition at line 255 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mc_cs_n

mc_cs_n in std_logic_vector ( CS_WIDTH * nCS_PER_RANK * nCK_PER_CLK - 1 downto 0 )
Port

Definition at line 256 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mc_reset_n

mc_reset_n in std_logic
Port

Definition at line 257 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mc_odt

mc_odt in std_logic_vector ( 1 downto 0 )
Port

Definition at line 258 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mc_cke

mc_cke in std_logic_vector ( nCK_PER_CLK - 1 downto 0 )
Port

Definition at line 259 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mc_aux_out0

mc_aux_out0 in std_logic_vector ( 3 downto 0 )
Port

Definition at line 261 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mc_aux_out1

mc_aux_out1 in std_logic_vector ( 3 downto 0 )
Port

Definition at line 262 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mc_cmd_wren

mc_cmd_wren in std_logic
Port

Definition at line 263 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mc_ctl_wren

mc_ctl_wren in std_logic
Port

Definition at line 264 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mc_cmd

mc_cmd in std_logic_vector ( 2 downto 0 )
Port

Definition at line 265 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mc_cas_slot

mc_cas_slot in std_logic_vector ( 1 downto 0 )
Port

Definition at line 266 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mc_data_offset

mc_data_offset in std_logic_vector ( 5 downto 0 )
Port

Definition at line 267 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mc_data_offset_1

mc_data_offset_1 in std_logic_vector ( 5 downto 0 )
Port

Definition at line 268 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mc_data_offset_2

mc_data_offset_2 in std_logic_vector ( 5 downto 0 )
Port

Definition at line 269 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mc_rank_cnt

mc_rank_cnt in std_logic_vector ( 1 downto 0 )
Port

Definition at line 270 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mc_wrdata_en

mc_wrdata_en in std_logic
Port

Definition at line 272 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mc_wrdata

mc_wrdata in std_logic_vector ( 2 * nCK_PER_CLK * DQ_WIDTH - 1 downto 0 )
Port

Definition at line 273 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mc_wrdata_mask

mc_wrdata_mask in std_logic_vector ( ( 2 * nCK_PER_CLK * ( DQ_WIDTH / 8 ) ) - 1 downto 0 )
Port

Definition at line 274 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ idle

idle in std_logic
Port

Definition at line 275 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ddr_addr

ddr_addr out std_logic_vector ( ROW_WIDTH - 1 downto 0 )
Port

Definition at line 277 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ddr_ba

ddr_ba out std_logic_vector ( BANK_WIDTH - 1 downto 0 )
Port

Definition at line 278 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ddr_cas_n

ddr_cas_n out std_logic
Port

Definition at line 279 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ddr_ck_n

ddr_ck_n out std_logic_vector ( CK_WIDTH - 1 downto 0 )
Port

Definition at line 280 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ddr_ck

ddr_ck out std_logic_vector ( CK_WIDTH - 1 downto 0 )
Port

Definition at line 281 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ddr_cke

ddr_cke out std_logic_vector ( CKE_WIDTH - 1 downto 0 )
Port

Definition at line 282 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ddr_cs_n

ddr_cs_n out std_logic_vector ( ( CS_WIDTH * nCS_PER_RANK ) - 1 downto 0 )
Port

Definition at line 283 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ddr_dm

ddr_dm out std_logic_vector ( DM_WIDTH - 1 downto 0 )
Port

Definition at line 284 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ddr_odt

ddr_odt out std_logic_vector ( ODT_WIDTH - 1 downto 0 )
Port

Definition at line 285 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ddr_ras_n

ddr_ras_n out std_logic
Port

Definition at line 286 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ddr_reset_n

ddr_reset_n out std_logic
Port

Definition at line 287 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ddr_parity

ddr_parity out std_logic
Port

Definition at line 288 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ddr_we_n

ddr_we_n out std_logic
Port

Definition at line 289 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ddr_dq

ddr_dq inout std_logic_vector ( DQ_WIDTH - 1 downto 0 )
Port

Definition at line 290 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ddr_dqs_n

ddr_dqs_n inout std_logic_vector ( DQS_WIDTH - 1 downto 0 )
Port

Definition at line 291 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ddr_dqs

ddr_dqs inout std_logic_vector ( DQS_WIDTH - 1 downto 0 )
Port

Definition at line 292 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ psen

psen out std_logic
Port

Definition at line 294 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ psincdec

psincdec out std_logic
Port

Definition at line 295 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ psdone

psdone in std_logic
Port

Definition at line 296 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ calib_tap_req

calib_tap_req out std_logic
Port

Definition at line 297 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ calib_tap_load

calib_tap_load in std_logic
Port

Definition at line 298 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ calib_tap_addr

calib_tap_addr in std_logic_vector ( 6 downto 0 )
Port

Definition at line 299 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ calib_tap_val

calib_tap_val in std_logic_vector ( 7 downto 0 )
Port

Definition at line 300 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ calib_tap_load_done

calib_tap_load_done in std_logic
Port

Definition at line 301 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_calib_top

dbg_calib_top out std_logic_vector ( 255 downto 0 )
Port

Definition at line 303 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_cpt_first_edge_cnt

dbg_cpt_first_edge_cnt out std_logic_vector ( 6 * DQS_WIDTH * RANKS - 1 downto 0 )
Port

Definition at line 304 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_cpt_second_edge_cnt

dbg_cpt_second_edge_cnt out std_logic_vector ( 6 * DQS_WIDTH * RANKS - 1 downto 0 )
Port

Definition at line 305 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_cpt_tap_cnt

dbg_cpt_tap_cnt out std_logic_vector ( 6 * DQS_WIDTH * RANKS - 1 downto 0 )
Port

Definition at line 306 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_dq_idelay_tap_cnt

dbg_dq_idelay_tap_cnt out std_logic_vector ( 5 * DQS_WIDTH * RANKS - 1 downto 0 )
Port

Definition at line 307 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_phy_rdlvl

dbg_phy_rdlvl out std_logic_vector ( 255 downto 0 )
Port

Definition at line 308 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_phy_wrcal

dbg_phy_wrcal out std_logic_vector ( 99 downto 0 )
Port

Definition at line 309 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_final_po_fine_tap_cnt

dbg_final_po_fine_tap_cnt out std_logic_vector ( 6 * DQS_WIDTH - 1 downto 0 )
Port

Definition at line 310 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_final_po_coarse_tap_cnt

dbg_final_po_coarse_tap_cnt out std_logic_vector ( 3 * DQS_WIDTH - 1 downto 0 )
Port

Definition at line 311 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_rd_data_edge_detect

dbg_rd_data_edge_detect out std_logic_vector ( DQS_WIDTH - 1 downto 0 )
Port

Definition at line 312 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_rddata

dbg_rddata out std_logic_vector ( 2 * nCK_PER_CLK * DQ_WIDTH - 1 downto 0 )
Port

Definition at line 313 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_rddata_valid

dbg_rddata_valid out std_logic
Port

Definition at line 314 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_rdlvl_done

dbg_rdlvl_done out std_logic_vector ( 1 downto 0 )
Port

Definition at line 315 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_rdlvl_err

dbg_rdlvl_err out std_logic_vector ( 1 downto 0 )
Port

Definition at line 316 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_rdlvl_start

dbg_rdlvl_start out std_logic_vector ( 1 downto 0 )
Port

Definition at line 317 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_tap_cnt_during_wrlvl

dbg_tap_cnt_during_wrlvl out std_logic_vector ( 5 downto 0 )
Port

Definition at line 318 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_wl_edge_detect_valid

dbg_wl_edge_detect_valid out std_logic
Port

Definition at line 319 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_wrlvl_done

dbg_wrlvl_done out std_logic
Port

Definition at line 320 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_wrlvl_err

dbg_wrlvl_err out std_logic
Port

Definition at line 321 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_wrlvl_start

dbg_wrlvl_start out std_logic
Port

Definition at line 322 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_wrlvl_fine_tap_cnt

dbg_wrlvl_fine_tap_cnt out std_logic_vector ( 6 * DQS_WIDTH - 1 downto 0 )
Port

Definition at line 323 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_wrlvl_coarse_tap_cnt

dbg_wrlvl_coarse_tap_cnt out std_logic_vector ( 3 * DQS_WIDTH - 1 downto 0 )
Port

Definition at line 324 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_phy_wrlvl

dbg_phy_wrlvl out std_logic_vector ( 255 downto 0 )
Port

Definition at line 325 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_pi_phaselock_start

dbg_pi_phaselock_start out std_logic
Port

Definition at line 326 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_pi_phaselocked_done

dbg_pi_phaselocked_done out std_logic
Port

Definition at line 327 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_pi_phaselock_err

dbg_pi_phaselock_err out std_logic
Port

Definition at line 328 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_pi_phase_locked_phy4lanes

dbg_pi_phase_locked_phy4lanes out std_logic_vector ( 11 downto 0 )
Port

Definition at line 329 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_pi_dqsfound_start

dbg_pi_dqsfound_start out std_logic
Port

Definition at line 330 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_pi_dqsfound_done

dbg_pi_dqsfound_done out std_logic
Port

Definition at line 331 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_pi_dqsfound_err

dbg_pi_dqsfound_err out std_logic
Port

Definition at line 332 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_pi_dqs_found_lanes_phy4lanes

dbg_pi_dqs_found_lanes_phy4lanes out std_logic_vector ( 11 downto 0 )
Port

Definition at line 333 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_wrcal_start

dbg_wrcal_start out std_logic
Port

Definition at line 334 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_wrcal_done

dbg_wrcal_done out std_logic
Port

Definition at line 335 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_wrcal_err

dbg_wrcal_err out std_logic
Port

Definition at line 336 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_poc

dbg_poc out std_logic_vector ( 1023 downto 0 )
Port

Definition at line 337 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ phy_mc_ctl_full

phy_mc_ctl_full out std_logic
Port

Definition at line 339 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ phy_mc_cmd_full

phy_mc_cmd_full out std_logic
Port

Definition at line 340 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ phy_mc_data_full

phy_mc_data_full out std_logic
Port

Definition at line 341 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ init_calib_complete

init_calib_complete out std_logic
Port

Definition at line 343 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ init_wrcal_complete

init_wrcal_complete out std_logic
Port

Definition at line 344 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ calib_rd_data_offset_0

calib_rd_data_offset_0 out std_logic_vector ( 6 * RANKS - 1 downto 0 )
Port

Definition at line 345 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ calib_rd_data_offset_1

calib_rd_data_offset_1 out std_logic_vector ( 6 * RANKS - 1 downto 0 )
Port

Definition at line 346 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ calib_rd_data_offset_2

calib_rd_data_offset_2 out std_logic_vector ( 6 * RANKS - 1 downto 0 )
Port

Definition at line 347 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ phy_rddata_valid

phy_rddata_valid out std_logic
Port

Definition at line 348 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ phy_rd_data

phy_rd_data out std_logic_vector ( 2 * nCK_PER_CLK * DQ_WIDTH - 1 downto 0 )
Port

Definition at line 349 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ref_dll_lock

ref_dll_lock out std_logic
Port

Definition at line 351 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ rst_phaser_ref

rst_phaser_ref in std_logic
Port

Definition at line 352 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_rd_data_offset

dbg_rd_data_offset out std_logic_vector ( 6 * RANKS - 1 downto 0 )
Port

Definition at line 353 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_phy_init

dbg_phy_init out std_logic_vector ( 255 downto 0 )
Port

Definition at line 354 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_prbs_rdlvl

dbg_prbs_rdlvl out std_logic_vector ( 255 downto 0 )
Port

Definition at line 355 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_dqs_found_cal

dbg_dqs_found_cal out std_logic_vector ( 255 downto 0 )
Port

Definition at line 356 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_pi_counter_read_val

dbg_pi_counter_read_val out std_logic_vector ( 5 downto 0 )
Port

Definition at line 357 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_po_counter_read_val

dbg_po_counter_read_val out std_logic_vector ( 8 downto 0 )
Port

Definition at line 358 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_oclkdelay_calib_start

dbg_oclkdelay_calib_start out std_logic
Port

Definition at line 359 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_oclkdelay_calib_done

dbg_oclkdelay_calib_done out std_logic
Port

Definition at line 360 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_phy_oclkdelay_cal

dbg_phy_oclkdelay_cal out std_logic_vector ( 255 downto 0 )
Port

Definition at line 361 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_oclkdelay_rd_data

dbg_oclkdelay_rd_data out std_logic_vector ( DRAM_WIDTH * 16 - 1 downto 0 )
Port

Definition at line 362 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ prbs_final_dqs_tap_cnt_r

prbs_final_dqs_tap_cnt_r out std_logic_vector ( 6 * DQS_WIDTH * RANKS - 1 downto 0 )
Port

Definition at line 363 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_prbs_first_edge_taps

dbg_prbs_first_edge_taps out std_logic_vector ( 6 * DQS_WIDTH * RANKS - 1 downto 0 )
Port

Definition at line 364 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_prbs_second_edge_taps

dbg_prbs_second_edge_taps out std_logic_vector ( 6 * DQS_WIDTH * RANKS - 1 downto 0 )
Port

Definition at line 367 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ieee

ieee
Library

Definition at line 68 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ std_logic_1164

std_logic_1164
use clause

Definition at line 69 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ numeric_std

numeric_std
use clause

Definition at line 70 of file mig_7series_v4_2_ddr_phy_top.vhd.

The documentation for this design unit was generated from the following files: