w11 - vhd 0.794
W11 CPU core and support modules
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crc16.vhd
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1-- $Id: crc16.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2014- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: crc16 - syn
7-- Description: 16bit CRC generator, use CCITT polynomial
8-- x^16 + x^12 + x^5 + 1 (0x1021)
9--
10--
11-- Dependencies: -
12-- Test bench: -
13-- Target Devices: generic
14-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31
15--
16-- Synthesized (xst):
17-- Date Rev ise Target flop lutl lutm slic t peri
18-- 2014-09-27 595 14.7 131013 xc6slx16-2 16 16 - 4
19--
20-- Revision History:
21-- Date Rev Version Comment
22-- 2014-09-27 595 1.0 Initial version
23------------------------------------------------------------------------------
24
25library ieee;
26use ieee.std_logic_1164.all;
27
28use work.slvtypes.all;
29use work.comlib.all;
30
31entity crc16 is -- crc-16 generator, checker
32 generic (
33 INIT: slv16 := (others=>'0')); -- initial state of crc register
34 port (
35 CLK : in slbit; -- clock
36 RESET : in slbit; -- reset
37 ENA : in slbit; -- update enable
38 DI : in slv8; -- input data
39 CRC : out slv16 -- crc code
40 );
41end crc16;
42
43
44architecture syn of crc16 is
45 signal R_CRC : slv16 := INIT; -- state registers
46begin
47
48 proc_regs: process (CLK)
49 begin
50
51 if rising_edge(CLK) then
52 if RESET = '1' then
53 R_CRC <= INIT;
54 else
55 if ENA = '1' then
56 R_CRC <= crc16_update(R_CRC, DI);
57 end if;
58 end if;
59 end if;
60
61 end process proc_regs;
62
63 CRC <= R_CRC;
64
65end syn;
slv16 := INIT R_CRC
Definition: crc16.vhd:45
Definition: crc16.vhd:31
in RESET slbit
Definition: crc16.vhd:36
in ENA slbit
Definition: crc16.vhd:37
out CRC slv16
Definition: crc16.vhd:40
INIT slv16 :=( others => '0')
Definition: crc16.vhd:33
in CLK slbit
Definition: crc16.vhd:35
in DI slv8
Definition: crc16.vhd:38
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40