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W11 CPU core and support modules
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crc16.vhd
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-- $Id: crc16.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2014- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: crc16 - syn
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-- Description: 16bit CRC generator, use CCITT polynomial
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-- x^16 + x^12 + x^5 + 1 (0x1021)
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--
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31
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--
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2014-09-27 595 14.7 131013 xc6slx16-2 16 16 - 4
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2014-09-27 595 1.0 Initial version
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------------------------------------------------------------------------------
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library
ieee
;
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use
ieee.std_logic_1164.
all
;
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use
work.
slvtypes
.
all
;
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use
work.
comlib
.
all
;
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entity
crc16
is
-- crc-16 generator, checker
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generic
(
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INIT
:
slv16
:=
(
others
=
>
'
0
'
)
)
;
-- initial state of crc register
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port
(
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CLK
:
in
slbit
;
-- clock
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RESET
:
in
slbit
;
-- reset
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ENA
:
in
slbit
;
-- update enable
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DI
:
in
slv8
;
-- input data
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CRC
:
out
slv16
-- crc code
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)
;
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end
crc16
;
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architecture
syn
of
crc16
is
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signal
R_CRC
:
slv16
:=
INIT
;
-- state registers
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begin
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proc_regs:
process
(
CLK
)
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begin
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if
rising_edge
(
CLK
)
then
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if
RESET
=
'
1
'
then
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R_CRC
<=
INIT
;
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else
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if
ENA
=
'
1
'
then
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R_CRC
<=
crc16_update
(
R_CRC
,
DI
)
;
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end
if
;
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end
if
;
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end
if
;
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end
process
proc_regs
;
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CRC
<=
R_CRC
;
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end
syn;
comlib
Definition:
comlib.vhd:33
crc16.syn
Definition:
crc16.vhd:44
crc16.syn.R_CRC
slv16 := INIT R_CRC
Definition:
crc16.vhd:45
crc16
Definition:
crc16.vhd:31
crc16.RESET
in RESET slbit
Definition:
crc16.vhd:36
crc16.ENA
in ENA slbit
Definition:
crc16.vhd:37
crc16.CRC
out CRC slv16
Definition:
crc16.vhd:40
crc16.INIT
INIT slv16 :=( others => '0')
Definition:
crc16.vhd:33
crc16.CLK
in CLK slbit
Definition:
crc16.vhd:35
crc16.DI
in DI slv8
Definition:
crc16.vhd:38
slvtypes
Definition:
slvtypes.vhd:28
slvtypes.slv16
std_logic_vector( 15 downto 0) slv16
Definition:
slvtypes.vhd:48
slvtypes.slbit
std_logic slbit
Definition:
slvtypes.vhd:30
slvtypes.slv8
std_logic_vector( 7 downto 0) slv8
Definition:
slvtypes.vhd:40
vlib
comlib
crc16.vhd
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