w11 - vhd 0.794
W11 CPU core and support modules
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fx2lib.vhd
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1-- $Id: fx2lib.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2011-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Package Name: fx2lib
7-- Description: Cypress ez-usb fx2 support
8--
9-- Dependencies: -
10-- Tool versions: xst 12.1-14.7; ghdl 0.26-0.34
11--
12-- Revision History:
13-- Date Rev Version Comment
14-- 2017-04-30 888 1.5 add fsm_* monitor lines
15-- 2015-01-25 638 1.4 retire fx2_2fifoctl_as
16-- 2012-01-14 453 1.3 use afull/aempty logic instead of exporting size
17-- 2012-01-03 449 1.2.1 reorganize fx2ctl_moni; hardcode ep's
18-- 2012-01-01 448 1.2 add fx2_2fifoctl_ic
19-- 2011-12-25 445 1.1 change pktend iface in fx2_2fifoctl_as
20-- 2011-07-17 394 1.0.1 add c_fifo_epx and fx2ctl_moni_type
21-- 2011-07-07 389 1.0 Initial version
22------------------------------------------------------------------------------
23
24library ieee;
25use ieee.std_logic_1164.all;
26
27use work.slvtypes.all;
28
29package fx2lib is
30
31 constant c_fifo_ep2 : slv2 := "00"; -- fifo address: end point 2
32 constant c_fifo_ep4 : slv2 := "01"; -- fifo address: end point 4
33 constant c_fifo_ep6 : slv2 := "10"; -- fifo address: end point 6
34 constant c_fifo_ep8 : slv2 := "11"; -- fifo address: end point 8
35
36 type fx2ctl_moni_type is record -- fx2ctl monitor port
37 fifo_ep4 : slbit; -- fifo 1 (ep4) active;
38 fifo_ep6 : slbit; -- fifo 2 (ep6) active;
39 fifo_ep8 : slbit; -- fifo 3 (ep8) active;
40 flag_ep4_empty : slbit; -- ep4 empty flag (latched);
41 flag_ep4_almost : slbit; -- ep4 almost empty flag (latched);
42 flag_ep6_full : slbit; -- ep6 full flag (latched);
43 flag_ep6_almost : slbit; -- ep6 almost full flag (latched);
44 flag_ep8_full : slbit; -- ep8 full flag (latched);
45 flag_ep8_almost : slbit; -- ep8 almost full flag (latched);
46 slrd : slbit; -- read strobe
47 slwr : slbit; -- write strobe
48 pktend : slbit; -- pktend strobe
49 fsm_idle : slbit; -- fsm: in s_idle
50 fsm_prep : slbit; -- fsm: in s_*prep*
51 fsm_disp : slbit; -- fsm: in s_*disp*
52 fsm_pipe : slbit; -- fsm: in s_rxpipe
53 fsm_rx : slbit; -- fsm: in s_rx*
54 fsm_tx : slbit; -- fsm: in s_tx*
55 fsm_tx2 : slbit; -- fsm: in s_tx2*
56 end record fx2ctl_moni_type;
57
59 '0','0','0', -- fifo_ep[468]
60 '0','0', -- flag_ep4_(empty|almost)
61 '0','0', -- flag_ep6_(full|almost)
62 '0','0', -- flag_ep8_(full|almost)
63 '0','0','0', -- slrd, slwr, pktend
64 '0','0','0','0', -- fsm_(idle|prep|disp|pipe)
65 '0','0','0' -- fsm_(rx|tx|tx2)
66 );
67
68
69-- -------------------------------------
70component fx2_2fifoctl_ic is -- EZ-USB FX2 controller(2 fifo; int clk)
71 generic (
72 RXFAWIDTH : positive := 5; -- receive fifo address width
73 TXFAWIDTH : positive := 5; -- transmit fifo address width
74 PETOWIDTH : positive := 7; -- packet end time-out counter width
75 CCWIDTH : positive := 5; -- chunk counter width
76 RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
77 TXAFULL_THRES : natural := 1); -- threshold for tx afull flag
78 port (
79 CLK : in slbit; -- clock
80 RESET : in slbit := '0'; -- reset
81 RXDATA : out slv8; -- receive data out
82 RXVAL : out slbit; -- receive data valid
83 RXHOLD : in slbit; -- receive data hold
84 RXAEMPTY : out slbit; -- receive almost empty flag
85 TXDATA : in slv8; -- transmit data in
86 TXENA : in slbit; -- transmit data enable
87 TXBUSY : out slbit; -- transmit data busy
88 TXAFULL : out slbit; -- transmit almost full flag
89 MONI : out fx2ctl_moni_type; -- monitor port data
90 I_FX2_IFCLK : in slbit; -- fx2: interface clock
91 O_FX2_FIFO : out slv2; -- fx2: fifo address
92 I_FX2_FLAG : in slv4; -- fx2: fifo flags
93 O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
94 O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
95 O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
96 O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
97 IO_FX2_DATA : inout slv8 -- fx2: data lines
98 );
99end component;
100
101component fx2_3fifoctl_ic is -- EZ-USB FX2 controller(3 fifo; int clk)
102 generic (
103 RXFAWIDTH : positive := 5; -- receive fifo address width
104 TXFAWIDTH : positive := 5; -- transmit fifo address width
105 PETOWIDTH : positive := 7; -- packet end time-out counter width
106 CCWIDTH : positive := 5; -- chunk counter width
107 RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
108 TXAFULL_THRES : natural := 1; -- threshold for tx afull flag
109 TX2AFULL_THRES : natural := 1); -- threshold for tx2 afull flag
110 port (
111 CLK : in slbit; -- clock
112 RESET : in slbit := '0'; -- reset
113 RXDATA : out slv8; -- receive data out
114 RXVAL : out slbit; -- receive data valid
115 RXHOLD : in slbit; -- receive data hold
116 RXAEMPTY : out slbit; -- receive almost empty flag
117 TXDATA : in slv8; -- transmit 1 data in
118 TXENA : in slbit; -- transmit 1 data enable
119 TXBUSY : out slbit; -- transmit 1 data busy
120 TXAFULL : out slbit; -- transmit 1 almost full flag
121 TX2DATA : in slv8; -- transmit 2 data in
122 TX2ENA : in slbit; -- transmit 2 data enable
123 TX2BUSY : out slbit; -- transmit 2 data busy
124 TX2AFULL : out slbit; -- transmit 2 almost full flag
125 MONI : out fx2ctl_moni_type; -- monitor port data
126 I_FX2_IFCLK : in slbit; -- fx2: interface clock
127 O_FX2_FIFO : out slv2; -- fx2: fifo address
128 I_FX2_FLAG : in slv4; -- fx2: fifo flags
129 O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
130 O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
131 O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
132 O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
133 IO_FX2_DATA : inout slv8 -- fx2: data lines
134 );
135end component;
136
137end package fx2lib;
inout IO_FX2_DATA slv8
in I_FX2_IFCLK slbit
out O_FX2_PKTEND_N slbit
out TXAFULL slbit
RXAEMPTY_THRES natural := 1
CCWIDTH positive := 5
out O_FX2_SLWR_N slbit
out O_FX2_FIFO slv2
PETOWIDTH positive := 7
TXFAWIDTH positive := 5
RXFAWIDTH positive := 5
out MONI fx2ctl_moni_type
out RXAEMPTY slbit
in RESET slbit := '0'
TXAFULL_THRES natural := 1
out O_FX2_SLRD_N slbit
out O_FX2_SLOE_N slbit
inout IO_FX2_DATA slv8
TX2AFULL_THRES natural := 1
in I_FX2_IFCLK slbit
out TX2AFULL slbit
out O_FX2_PKTEND_N slbit
out TXAFULL slbit
out TX2BUSY slbit
RXAEMPTY_THRES natural := 1
CCWIDTH positive := 5
out O_FX2_SLWR_N slbit
out O_FX2_FIFO slv2
PETOWIDTH positive := 7
TXFAWIDTH positive := 5
RXFAWIDTH positive := 5
out MONI fx2ctl_moni_type
out RXAEMPTY slbit
in RESET slbit := '0'
TXAFULL_THRES natural := 1
out O_FX2_SLRD_N slbit
out O_FX2_SLOE_N slbit
slv2 := "11" c_fifo_ep8
Definition: fx2lib.vhd:34
slv2 := "00" c_fifo_ep2
Definition: fx2lib.vhd:31
fx2ctl_moni_type :=( '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0') fx2ctl_moni_init
Definition: fx2lib.vhd:58
slv2 := "01" c_fifo_ep4
Definition: fx2lib.vhd:32
slv2 := "10" c_fifo_ep6
Definition: fx2lib.vhd:33
fx2ctl_moni_type
Definition: fx2lib.vhd:36
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34