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W11 CPU core and support modules
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gen_crc8_tbl.vhd
Go to the documentation of this file.
1
-- $Id: gen_crc8_tbl.vhd 1181 2019-07-08 17:00:50Z mueller $
2
-- SPDX-License-Identifier: GPL-3.0-or-later
3
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4
--
5
------------------------------------------------------------------------------
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-- Module Name: gen_crc8_tbl - sim
7
-- Description: stand-alone program to print crc8 transition table
8
--
9
-- Dependencies: comlib/crc8_update (function)
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--
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-- Revision History:
12
-- Date Rev Version Comment
13
-- 2011-09-17 410 1.1 now numeric_std clean; use function crc8_update
14
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-07-08 65 1.0 Initial version
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------------------------------------------------------------------------------
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18
library
ieee
;
19
use
ieee.std_logic_1164.
all
;
20
use
ieee.numeric_std.
all
;
21
use
std.textio.
all
;
22
23
use
work.
slvtypes
.
all
;
24
use
work.
comlib
.
all
;
25
26
entity
gen_crc8_tbl
is
27
end
gen_crc8_tbl
;
28
29
architecture
sim
of
gen_crc8_tbl
is
30
begin
31
32
process
33
variable
crc
:
slv8
:=
(
others
=
>
'
0
'
)
;
34
variable
dat
:
slv8
:=
(
others
=
>
'
0
'
)
;
35
variable
nxt
:
slv8
:=
(
others
=
>
'
0
'
)
;
36
variable
oline
:
line
;
37
begin
38
for
i
in
0
to
255
loop
39
crc
:=
(
others
=
>
'
0
'
)
;
40
dat
:=
slv
(
to_unsigned
(
i
,
8
)
)
;
41
nxt
:=
crc8_update
(
crc
,
dat
)
;
42
write
(
oline
,
to_integer
(
unsigned
(
nxt
)
)
,
right
,
4
)
;
43
if
i
/=
255
then
44
write
(
oline
,
string
'
(
","
)
)
;
45
end
if
;
46
if
(
i
mod
8
)
=
7
then
47
writeline
(
output
,
oline
)
;
48
end
if
;
49
end
loop
;
-- i
50
wait
;
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end
process
;
52
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end
sim;
comlib
Definition:
comlib.vhd:33
gen_crc8_tbl.sim
Definition:
gen_crc8_tbl.vhd:29
gen_crc8_tbl
Definition:
gen_crc8_tbl.vhd:26
slvtypes
Definition:
slvtypes.vhd:28
slvtypes.slv8
std_logic_vector( 7 downto 0) slv8
Definition:
slvtypes.vhd:40
slvtypes.slv
std_logic_vector slv
Definition:
slvtypes.vhd:31
vlib
comlib
misc
gen_crc8_tbl.vhd
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