w11 - vhd 0.794
W11 CPU core and support modules
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led_pulse_stretch.vhd
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1-- $Id: led_pulse_stretch.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2012- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: led_pulse_stretch - syn
7-- Description: pulse stretcher for leds
8--
9-- Dependencies: -
10-- Test bench: -
11-- Target Devices: generic
12-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
13-- Revision History:
14-- Date Rev Version Comment
15-- 2012-12-29 466 1.0 Initial version
16------------------------------------------------------------------------------
17
18library ieee;
19use ieee.std_logic_1164.all;
20use ieee.numeric_std.all;
21
22use work.slvtypes.all;
23
24entity led_pulse_stretch is -- pulse stretcher for leds
25 port (
26 CLK : in slbit; -- clock
27 CE_INT : in slbit; -- pulse time unit clock enable
28 RESET : in slbit := '0'; -- reset
29 DIN : in slbit; -- data in
30 POUT : out slbit -- pulse out
31 );
32end entity led_pulse_stretch;
33
34architecture syn of led_pulse_stretch is
35
36 type regs_type is record -- state registers
37 seen : slbit; -- DIN seen
38 busy : slbit; -- POUT busy
39 end record regs_type;
40
41 constant regs_init : regs_type := (
42 '0', -- seen
43 '0' -- busy
44 );
45
46 signal R_REGS : regs_type := regs_init; -- state registers
47 signal N_REGS : regs_type := regs_init; -- next value state regs
48
49begin
50
51 proc_regs: process (CLK)
52 begin
53
54 if rising_edge(CLK) then
55 if RESET = '1' then
57 else
58 R_REGS <= N_REGS;
59 end if;
60 end if;
61
62 end process proc_regs;
63
64 proc_next: process (R_REGS, CE_INT, DIN)
65 variable r : regs_type := regs_init;
66 variable n : regs_type := regs_init;
67
68 begin
69
70 r := R_REGS;
71 n := R_REGS;
72
73 if CE_INT='1' then
74 n.seen := DIN;
75 n.busy := r.seen;
76 else
77 if DIN='1' then
78 n.seen := '1';
79 end if;
80 end if;
81
82 N_REGS <= n;
83
84 POUT <= r.busy;
85
86 end process proc_next;
87
88end syn;
regs_type :=( '0', '0') regs_init
regs_type := regs_init N_REGS
regs_type := regs_init R_REGS
in RESET slbit := '0'
std_logic slbit
Definition: slvtypes.vhd:30