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W11 CPU core and support modules
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nexys2lib.vhd
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1-- $Id: nexys2lib.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2010-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Package Name: nexys2lib
7-- Description: Nexys 2 components
8--
9-- Dependencies: -
10-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
11--
12-- Revision History:
13-- Date Rev Version Comment
14-- 2013-01-01 467 1.4 add nexys2_cuff_aif, nexys2_fusp_cuff_aif
15-- 2011-12-23 444 1.3 remove clksys output hack
16-- 2011-11-26 433 1.2 remove n2_cram_* modules, now in nxcramlib
17-- 2011-11-23 432 1.1 remove O_FLA_CE_N port in cram controller/dummy
18-- 2010-11-13 338 1.0.2 add O_CLKSYS to aif's (DCM derived system clock)
19-- 2010-11-06 336 1.0.4 rename input pin CLK -> I_CLK50
20-- 2010-05-28 295 1.0.3 use _ADV_N also for n2_cram_dummy
21-- 2010-05-23 294 1.0.2 add n2_cram_dummy;
22-- 2010-05-23 293 1.0.1 use _ADV_N rather _ADV; add generic for memctl
23-- 2010-05-21 292 1.0 Initial version
24------------------------------------------------------------------------------
25
26library ieee;
27use ieee.std_logic_1164.all;
28
29use work.slvtypes.all;
30
31package nexys2lib is
32
33component nexys2_aif is -- NEXYS 2, abstract iface, base
34 port (
35 I_CLK50 : in slbit; -- 50 MHz board clock
36 I_RXD : in slbit; -- receive data (board view)
37 O_TXD : out slbit; -- transmit data (board view)
38 I_SWI : in slv8; -- n2 switches
39 I_BTN : in slv4; -- n2 buttons
40 O_LED : out slv8; -- n2 leds
41 O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
42 O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
43 O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
44 O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
45 O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
46 O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
47 O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
48 O_MEM_CLK : out slbit; -- cram: clock
49 O_MEM_CRE : out slbit; -- cram: command register enable
50 I_MEM_WAIT : in slbit; -- cram: mem wait
51 O_MEM_ADDR : out slv23; -- cram: address lines
52 IO_MEM_DATA : inout slv16; -- cram: data lines
53 O_FLA_CE_N : out slbit -- flash ce.. (act.low)
54 );
55end component;
56
57component nexys2_fusp_aif is -- NEXYS 2, abstract iface, base+fusp
58 port (
59 I_CLK50 : in slbit; -- 50 MHz board clock
60 I_RXD : in slbit; -- receive data (board view)
61 O_TXD : out slbit; -- transmit data (board view)
62 I_SWI : in slv8; -- n2 switches
63 I_BTN : in slv4; -- n2 buttons
64 O_LED : out slv8; -- n2 leds
65 O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
66 O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
67 O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
68 O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
69 O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
70 O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
71 O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
72 O_MEM_CLK : out slbit; -- cram: clock
73 O_MEM_CRE : out slbit; -- cram: command register enable
74 I_MEM_WAIT : in slbit; -- cram: mem wait
75 O_MEM_ADDR : out slv23; -- cram: address lines
76 IO_MEM_DATA : inout slv16; -- cram: data lines
77 O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
78 O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
79 I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
80 I_FUSP_RXD : in slbit; -- fusp: rs232 rx
81 O_FUSP_TXD : out slbit -- fusp: rs232 tx
82 );
83end component;
84
85component nexys2_cuff_aif is -- NEXYS 2, abstract iface, base+cuff
86 port (
87 I_CLK50 : in slbit; -- 50 MHz board clock
88 I_RXD : in slbit; -- receive data (board view)
89 O_TXD : out slbit; -- transmit data (board view)
90 I_SWI : in slv8; -- n2 switches
91 I_BTN : in slv4; -- n2 buttons
92 O_LED : out slv8; -- n2 leds
93 O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
94 O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
95 O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
96 O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
97 O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
98 O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
99 O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
100 O_MEM_CLK : out slbit; -- cram: clock
101 O_MEM_CRE : out slbit; -- cram: command register enable
102 I_MEM_WAIT : in slbit; -- cram: mem wait
103 O_MEM_ADDR : out slv23; -- cram: address lines
104 IO_MEM_DATA : inout slv16; -- cram: data lines
105 O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
106 I_FX2_IFCLK : in slbit; -- fx2: interface clock
107 O_FX2_FIFO : out slv2; -- fx2: fifo address
108 I_FX2_FLAG : in slv4; -- fx2: fifo flags
109 O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
110 O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
111 O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
112 O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
113 IO_FX2_DATA : inout slv8 -- fx2: data lines
114 );
115end component;
116
117component nexys2_fusp_cuff_aif is -- NEXYS 2, abstract iface, +fusp+cuff
118 port (
119 I_CLK50 : in slbit; -- 50 MHz board clock
120 I_RXD : in slbit; -- receive data (board view)
121 O_TXD : out slbit; -- transmit data (board view)
122 I_SWI : in slv8; -- n2 switches
123 I_BTN : in slv4; -- n2 buttons
124 O_LED : out slv8; -- n2 leds
125 O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
126 O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
127 O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
128 O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
129 O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
130 O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
131 O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
132 O_MEM_CLK : out slbit; -- cram: clock
133 O_MEM_CRE : out slbit; -- cram: command register enable
134 I_MEM_WAIT : in slbit; -- cram: mem wait
135 O_MEM_ADDR : out slv23; -- cram: address lines
136 IO_MEM_DATA : inout slv16; -- cram: data lines
137 O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
138 O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
139 I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
140 I_FUSP_RXD : in slbit; -- fusp: rs232 rx
141 O_FUSP_TXD : out slbit; -- fusp: rs232 tx
142 I_FX2_IFCLK : in slbit; -- fx2: interface clock
143 O_FX2_FIFO : out slv2; -- fx2: fifo address
144 I_FX2_FLAG : in slv4; -- fx2: fifo flags
145 O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
146 O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
147 O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
148 O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
149 IO_FX2_DATA : inout slv8 -- fx2: data lines
150 );
151end component;
152
153end package nexys2lib;