w11 - vhd 0.794
W11 CPU core and support modules
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nexys3_fusp_cuff_dummy.vhd
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1-- $Id: nexys3_fusp_cuff_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: nexys3_dummy - syn
7-- Description: nexys3 minimal target (base; serport loopback)
8--
9-- Dependencies: -
10-- To test: tb_nexys3
11-- Target Devices: generic
12-- Tool versions: xst 13.1; ghdl 0.29
13--
14-- Revision History:
15-- Date Rev Version Comment
16-- 2013-04-21 509 1.0 Initial version (derived nexys3_fusp_dummy)
17------------------------------------------------------------------------------
18
19library ieee;
20use ieee.std_logic_1164.all;
21
22use work.slvtypes.all;
23use work.nxcramlib.all;
24
25entity nexys3_fusp_cuff_dummy is -- NEXYS 3 dummy (+fusp+cuff; loopback)
26 -- implements nexys3_fusp_cuff_aif
27 port (
28 I_CLK100 : in slbit; -- 100 MHz board clock
29 I_RXD : in slbit; -- receive data (board view)
30 O_TXD : out slbit; -- transmit data (board view)
31 I_SWI : in slv8; -- n3 switches
32 I_BTN : in slv5; -- n3 buttons
33 O_LED : out slv8; -- n3 leds
34 O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
35 O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
36 O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
37 O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
38 O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
39 O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
40 O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
41 O_MEM_CLK : out slbit; -- cram: clock
42 O_MEM_CRE : out slbit; -- cram: command register enable
43 I_MEM_WAIT : in slbit; -- cram: mem wait
44 O_MEM_ADDR : out slv23; -- cram: address lines
45 IO_MEM_DATA : inout slv16; -- cram: data lines
46 O_PPCM_CE_N : out slbit; -- ppcm: ...
47 O_PPCM_RST_N : out slbit; -- ppcm: ...
48 O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
49 I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
50 I_FUSP_RXD : in slbit; -- fusp: rs232 rx
51 O_FUSP_TXD : out slbit; -- fusp: rs232 tx
52 I_FX2_IFCLK : in slbit; -- fx2: interface clock
53 O_FX2_FIFO : out slv2; -- fx2: fifo address
54 I_FX2_FLAG : in slv4; -- fx2: fifo flags
55 O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
56 O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
57 O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
58 O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
59 IO_FX2_DATA : inout slv8 -- fx2: data lines
60 );
62
63architecture syn of nexys3_fusp_cuff_dummy is
64
65begin
66
67 O_TXD <= I_RXD; -- loop back
70
71 O_FX2_SLRD_N <= '1'; -- keep fx2 iface quiet
72 O_FX2_SLWR_N <= '1';
73 O_FX2_SLOE_N <= '1';
74 O_FX2_PKTEND_N <= '1';
75
76 CRAM : nx_cram_dummy -- connect CRAM to protection dummy
77 port map (
78 O_MEM_CE_N => O_MEM_CE_N,
79 O_MEM_BE_N => O_MEM_BE_N,
80 O_MEM_WE_N => O_MEM_WE_N,
81 O_MEM_OE_N => O_MEM_OE_N,
82 O_MEM_ADV_N => O_MEM_ADV_N,
83 O_MEM_CLK => O_MEM_CLK,
84 O_MEM_CRE => O_MEM_CRE,
85 I_MEM_WAIT => I_MEM_WAIT,
86 O_MEM_ADDR => O_MEM_ADDR,
87 IO_MEM_DATA => IO_MEM_DATA
88 );
89
90 O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
91 O_PPCM_RST_N <= '1'; --
92
93end syn;
std_logic_vector( 22 downto 0) slv23
Definition: slvtypes.vhd:56
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34