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W11 CPU core and support modules
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nexys3_fusp_dummy.vhd
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1-- $Id: nexys3_fusp_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: nexys3_dummy - syn
7-- Description: nexys3 minimal target (base; serport loopback)
8--
9-- Dependencies: -
10-- To test: tb_nexys3
11-- Target Devices: generic
12-- Tool versions: xst 13.1; ghdl 0.29
13--
14-- Revision History:
15-- Date Rev Version Comment
16-- 2011-11-26 433 1.1 use nxcramlib
17-- 2011-11-25 432 1.0 Initial version (derived from nexys2_fusp_dummy)
18------------------------------------------------------------------------------
19
20library ieee;
21use ieee.std_logic_1164.all;
22
23use work.slvtypes.all;
24use work.nxcramlib.all;
25
26entity nexys3_fusp_dummy is -- NEXYS 3 dummy (base+fusp; loopback)
27 -- implements nexys3_fusp_aif
28 port (
29 I_CLK100 : in slbit; -- 100 MHz board clock
30 I_RXD : in slbit; -- receive data (board view)
31 O_TXD : out slbit; -- transmit data (board view)
32 I_SWI : in slv8; -- n3 switches
33 I_BTN : in slv5; -- n3 buttons
34 O_LED : out slv8; -- n3 leds
35 O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
36 O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
37 O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
38 O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
39 O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
40 O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
41 O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
42 O_MEM_CLK : out slbit; -- cram: clock
43 O_MEM_CRE : out slbit; -- cram: command register enable
44 I_MEM_WAIT : in slbit; -- cram: mem wait
45 O_MEM_ADDR : out slv23; -- cram: address lines
46 IO_MEM_DATA : inout slv16; -- cram: data lines
47 O_PPCM_CE_N : out slbit; -- ppcm: ...
48 O_PPCM_RST_N : out slbit; -- ppcm: ...
49 O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
50 I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
51 I_FUSP_RXD : in slbit; -- fusp: rs232 rx
52 O_FUSP_TXD : out slbit -- fusp: rs232 tx
53 );
55
56architecture syn of nexys3_fusp_dummy is
57
58begin
59
60 O_TXD <= I_RXD; -- loop back
63
64 CRAM : nx_cram_dummy -- connect CRAM to protection dummy
65 port map (
66 O_MEM_CE_N => O_MEM_CE_N,
67 O_MEM_BE_N => O_MEM_BE_N,
68 O_MEM_WE_N => O_MEM_WE_N,
69 O_MEM_OE_N => O_MEM_OE_N,
70 O_MEM_ADV_N => O_MEM_ADV_N,
71 O_MEM_CLK => O_MEM_CLK,
72 O_MEM_CRE => O_MEM_CRE,
73 I_MEM_WAIT => I_MEM_WAIT,
74 O_MEM_ADDR => O_MEM_ADDR,
75 IO_MEM_DATA => IO_MEM_DATA
76 );
77
78 O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
79 O_PPCM_RST_N <= '1'; --
80
81end syn;
inout IO_MEM_DATA slv16
std_logic_vector( 22 downto 0) slv23
Definition: slvtypes.vhd:56
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34