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W11 CPU core and support modules
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nexys3_fusp_dummy.vhd
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1
-- $Id: nexys3_fusp_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: nexys3_dummy - syn
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-- Description: nexys3 minimal target (base; serport loopback)
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--
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-- Dependencies: -
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-- To test: tb_nexys3
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-- Target Devices: generic
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-- Tool versions: xst 13.1; ghdl 0.29
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-11-26 433 1.1 use nxcramlib
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-- 2011-11-25 432 1.0 Initial version (derived from nexys2_fusp_dummy)
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------------------------------------------------------------------------------
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library
ieee
;
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use
ieee.std_logic_1164.
all
;
22
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use
work.
slvtypes
.
all
;
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use
work.
nxcramlib
.
all
;
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entity
nexys3_fusp_dummy
is
-- NEXYS 3 dummy (base+fusp; loopback)
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-- implements nexys3_fusp_aif
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port
(
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I_CLK100
:
in
slbit
;
-- 100 MHz board clock
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I_RXD
:
in
slbit
;
-- receive data (board view)
31
O_TXD
:
out
slbit
;
-- transmit data (board view)
32
I_SWI
:
in
slv8
;
-- n3 switches
33
I_BTN
:
in
slv5
;
-- n3 buttons
34
O_LED
:
out
slv8
;
-- n3 leds
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O_ANO_N
:
out
slv4
;
-- 7 segment disp: anodes (act.low)
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O_SEG_N
:
out
slv8
;
-- 7 segment disp: segments (act.low)
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O_MEM_CE_N
:
out
slbit
;
-- cram: chip enable (act.low)
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O_MEM_BE_N
:
out
slv2
;
-- cram: byte enables (act.low)
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O_MEM_WE_N
:
out
slbit
;
-- cram: write enable (act.low)
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O_MEM_OE_N
:
out
slbit
;
-- cram: output enable (act.low)
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O_MEM_ADV_N
:
out
slbit
;
-- cram: address valid (act.low)
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O_MEM_CLK
:
out
slbit
;
-- cram: clock
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O_MEM_CRE
:
out
slbit
;
-- cram: command register enable
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I_MEM_WAIT
:
in
slbit
;
-- cram: mem wait
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O_MEM_ADDR
:
out
slv23
;
-- cram: address lines
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IO_MEM_DATA
:
inout
slv16
;
-- cram: data lines
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O_PPCM_CE_N
:
out
slbit
;
-- ppcm: ...
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O_PPCM_RST_N
:
out
slbit
;
-- ppcm: ...
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O_FUSP_RTS_N
:
out
slbit
;
-- fusp: rs232 rts_n
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I_FUSP_CTS_N
:
in
slbit
;
-- fusp: rs232 cts_n
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I_FUSP_RXD
:
in
slbit
;
-- fusp: rs232 rx
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O_FUSP_TXD
:
out
slbit
-- fusp: rs232 tx
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)
;
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end
nexys3_fusp_dummy
;
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architecture
syn
of
nexys3_fusp_dummy
is
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begin
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O_TXD
<=
I_RXD
;
-- loop back
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O_FUSP_TXD
<=
I_FUSP_RXD
;
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O_FUSP_RTS_N
<=
I_FUSP_CTS_N
;
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CRAM :
nx_cram_dummy
-- connect CRAM
to
protection dummy
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port
map
(
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O_MEM_CE_N =>
O_MEM_CE_N
,
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O_MEM_BE_N =>
O_MEM_BE_N
,
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O_MEM_WE_N =>
O_MEM_WE_N
,
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O_MEM_OE_N =>
O_MEM_OE_N
,
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O_MEM_ADV_N =>
O_MEM_ADV_N
,
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O_MEM_CLK =>
O_MEM_CLK
,
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O_MEM_CRE =>
O_MEM_CRE
,
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I_MEM_WAIT =>
I_MEM_WAIT
,
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O_MEM_ADDR =>
O_MEM_ADDR
,
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IO_MEM_DATA =>
IO_MEM_DATA
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)
;
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O_PPCM_CE_N
<=
'
1
'
;
-- keep parallel PCM memory disabled
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O_PPCM_RST_N
<=
'
1
'
;
--
80
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end
syn
;
nexys3_fusp_dummy.syn
Definition:
nexys3_fusp_dummy.vhd:56
nexys3_fusp_dummy
Definition:
nexys3_fusp_dummy.vhd:26
nexys3_fusp_dummy.O_FUSP_TXD
out O_FUSP_TXD slbit
Definition:
nexys3_fusp_dummy.vhd:53
nexys3_fusp_dummy.O_TXD
out O_TXD slbit
Definition:
nexys3_fusp_dummy.vhd:31
nexys3_fusp_dummy.O_FUSP_RTS_N
out O_FUSP_RTS_N slbit
Definition:
nexys3_fusp_dummy.vhd:49
nexys3_fusp_dummy.I_RXD
in I_RXD slbit
Definition:
nexys3_fusp_dummy.vhd:30
nexys3_fusp_dummy.O_PPCM_CE_N
out O_PPCM_CE_N slbit
Definition:
nexys3_fusp_dummy.vhd:47
nexys3_fusp_dummy.O_MEM_WE_N
out O_MEM_WE_N slbit
Definition:
nexys3_fusp_dummy.vhd:39
nexys3_fusp_dummy.O_LED
out O_LED slv8
Definition:
nexys3_fusp_dummy.vhd:34
nexys3_fusp_dummy.I_BTN
in I_BTN slv5
Definition:
nexys3_fusp_dummy.vhd:33
nexys3_fusp_dummy.I_FUSP_CTS_N
in I_FUSP_CTS_N slbit
Definition:
nexys3_fusp_dummy.vhd:50
nexys3_fusp_dummy.O_PPCM_RST_N
out O_PPCM_RST_N slbit
Definition:
nexys3_fusp_dummy.vhd:48
nexys3_fusp_dummy.O_MEM_CE_N
out O_MEM_CE_N slbit
Definition:
nexys3_fusp_dummy.vhd:37
nexys3_fusp_dummy.O_SEG_N
out O_SEG_N slv8
Definition:
nexys3_fusp_dummy.vhd:36
nexys3_fusp_dummy.I_FUSP_RXD
in I_FUSP_RXD slbit
Definition:
nexys3_fusp_dummy.vhd:51
nexys3_fusp_dummy.I_MEM_WAIT
in I_MEM_WAIT slbit
Definition:
nexys3_fusp_dummy.vhd:44
nexys3_fusp_dummy.I_CLK100
in I_CLK100 slbit
Definition:
nexys3_fusp_dummy.vhd:29
nexys3_fusp_dummy.O_MEM_OE_N
out O_MEM_OE_N slbit
Definition:
nexys3_fusp_dummy.vhd:40
nexys3_fusp_dummy.O_MEM_CLK
out O_MEM_CLK slbit
Definition:
nexys3_fusp_dummy.vhd:42
nexys3_fusp_dummy.O_MEM_ADV_N
out O_MEM_ADV_N slbit
Definition:
nexys3_fusp_dummy.vhd:41
nexys3_fusp_dummy.O_MEM_ADDR
out O_MEM_ADDR slv23
Definition:
nexys3_fusp_dummy.vhd:45
nexys3_fusp_dummy.O_MEM_BE_N
out O_MEM_BE_N slv2
Definition:
nexys3_fusp_dummy.vhd:38
nexys3_fusp_dummy.IO_MEM_DATA
inout IO_MEM_DATA slv16
Definition:
nexys3_fusp_dummy.vhd:46
nexys3_fusp_dummy.O_MEM_CRE
out O_MEM_CRE slbit
Definition:
nexys3_fusp_dummy.vhd:43
nexys3_fusp_dummy.I_SWI
in I_SWI slv8
Definition:
nexys3_fusp_dummy.vhd:32
nexys3_fusp_dummy.O_ANO_N
out O_ANO_N slv4
Definition:
nexys3_fusp_dummy.vhd:35
nx_cram_dummy
Definition:
nx_cram_dummy.vhd:26
nxcramlib
Definition:
nxcramlib.vhd:23
slvtypes
Definition:
slvtypes.vhd:28
slvtypes.slv23
std_logic_vector( 22 downto 0) slv23
Definition:
slvtypes.vhd:56
slvtypes.slv4
std_logic_vector( 3 downto 0) slv4
Definition:
slvtypes.vhd:36
slvtypes.slv5
std_logic_vector( 4 downto 0) slv5
Definition:
slvtypes.vhd:37
slvtypes.slv16
std_logic_vector( 15 downto 0) slv16
Definition:
slvtypes.vhd:48
slvtypes.slbit
std_logic slbit
Definition:
slvtypes.vhd:30
slvtypes.slv8
std_logic_vector( 7 downto 0) slv8
Definition:
slvtypes.vhd:40
slvtypes.slv2
std_logic_vector( 1 downto 0) slv2
Definition:
slvtypes.vhd:34
bplib
nexys3
tb
nexys3_fusp_dummy.vhd
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