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nexys3lib.vhd
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1-- $Id: nexys3lib.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Package Name: nexys3lib
7-- Description: Nexys 3 components
8--
9-- Dependencies: -
10-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
11--
12-- Revision History:
13-- Date Rev Version Comment
14-- 2013-04-21 509 1.1 add nexys3_cuff_aif, nexys3_fusp_cuff_aif
15-- 2011-11-25 432 1.0 Initial version
16------------------------------------------------------------------------------
17
18library ieee;
19use ieee.std_logic_1164.all;
20
21use work.slvtypes.all;
22
23package nexys3lib is
24
25component nexys3_aif is -- NEXYS 3, abstract iface, base
26 port (
27 I_CLK100 : in slbit; -- 100 MHz clock
28 I_RXD : in slbit; -- receive data (board view)
29 O_TXD : out slbit; -- transmit data (board view)
30 I_SWI : in slv8; -- n3 switches
31 I_BTN : in slv5; -- n3 buttons
32 O_LED : out slv8; -- n3 leds
33 O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
34 O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
35 O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
36 O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
37 O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
38 O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
39 O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
40 O_MEM_CLK : out slbit; -- cram: clock
41 O_MEM_CRE : out slbit; -- cram: command register enable
42 I_MEM_WAIT : in slbit; -- cram: mem wait
43 O_MEM_ADDR : out slv23; -- cram: address lines
44 IO_MEM_DATA : inout slv16; -- cram: data lines
45 O_PPCM_CE_N : out slbit; -- ppcm: ...
46 O_PPCM_RST_N : out slbit -- ppcm: ...
47 );
48end component;
49
50component nexys3_fusp_aif is -- NEXYS 3, abstract iface, base+fusp
51 port (
52 I_CLK100 : in slbit; -- 100 MHz clock
53 I_RXD : in slbit; -- receive data (board view)
54 O_TXD : out slbit; -- transmit data (board view)
55 I_SWI : in slv8; -- n3 switches
56 I_BTN : in slv5; -- n3 buttons
57 O_LED : out slv8; -- n3 leds
58 O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
59 O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
60 O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
61 O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
62 O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
63 O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
64 O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
65 O_MEM_CLK : out slbit; -- cram: clock
66 O_MEM_CRE : out slbit; -- cram: command register enable
67 I_MEM_WAIT : in slbit; -- cram: mem wait
68 O_MEM_ADDR : out slv23; -- cram: address lines
69 IO_MEM_DATA : inout slv16; -- cram: data lines
70 O_PPCM_CE_N : out slbit; -- ppcm: ...
71 O_PPCM_RST_N : out slbit; -- ppcm: ...
72 O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
73 I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
74 I_FUSP_RXD : in slbit; -- fusp: rs232 rx
75 O_FUSP_TXD : out slbit -- fusp: rs232 tx
76 );
77end component;
78
79component nexys3_cuff_aif is -- NEXYS 3, abstract iface, base+cuff
80 port (
81 I_CLK100 : in slbit; -- 100 MHz clock
82 I_RXD : in slbit; -- receive data (board view)
83 O_TXD : out slbit; -- transmit data (board view)
84 I_SWI : in slv8; -- n3 switches
85 I_BTN : in slv5; -- n3 buttons
86 O_LED : out slv8; -- n3 leds
87 O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
88 O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
89 O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
90 O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
91 O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
92 O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
93 O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
94 O_MEM_CLK : out slbit; -- cram: clock
95 O_MEM_CRE : out slbit; -- cram: command register enable
96 I_MEM_WAIT : in slbit; -- cram: mem wait
97 O_MEM_ADDR : out slv23; -- cram: address lines
98 IO_MEM_DATA : inout slv16; -- cram: data lines
99 O_PPCM_CE_N : out slbit; -- ppcm: ...
100 O_PPCM_RST_N : out slbit; -- ppcm: ...
101 I_FX2_IFCLK : in slbit; -- fx2: interface clock
102 O_FX2_FIFO : out slv2; -- fx2: fifo address
103 I_FX2_FLAG : in slv4; -- fx2: fifo flags
104 O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
105 O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
106 O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
107 O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
108 IO_FX2_DATA : inout slv8 -- fx2: data lines
109 );
110end component;
111
112component nexys3_fusp_cuff_aif is -- NEXYS 3, abstract iface, +fusp+cuff
113 port (
114 I_CLK100 : in slbit; -- 100 MHz clock
115 I_RXD : in slbit; -- receive data (board view)
116 O_TXD : out slbit; -- transmit data (board view)
117 I_SWI : in slv8; -- n3 switches
118 I_BTN : in slv5; -- n3 buttons
119 O_LED : out slv8; -- n3 leds
120 O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
121 O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
122 O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
123 O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
124 O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
125 O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
126 O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
127 O_MEM_CLK : out slbit; -- cram: clock
128 O_MEM_CRE : out slbit; -- cram: command register enable
129 I_MEM_WAIT : in slbit; -- cram: mem wait
130 O_MEM_ADDR : out slv23; -- cram: address lines
131 IO_MEM_DATA : inout slv16; -- cram: data lines
132 O_PPCM_CE_N : out slbit; -- ppcm: ...
133 O_PPCM_RST_N : out slbit; -- ppcm: ...
134 O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
135 I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
136 I_FUSP_RXD : in slbit; -- fusp: rs232 rx
137 O_FUSP_TXD : out slbit; -- fusp: rs232 tx
138 I_FX2_IFCLK : in slbit; -- fx2: interface clock
139 O_FX2_FIFO : out slv2; -- fx2: fifo address
140 I_FX2_FLAG : in slv4; -- fx2: fifo flags
141 O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
142 O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
143 O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
144 O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
145 IO_FX2_DATA : inout slv8 -- fx2: data lines
146 );
147end component;
148
149end package nexys3lib;