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W11 CPU core and support modules
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nexys4_cram_dummy.vhd
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1-- $Id: nexys4_cram_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: nexys4_cram_dummy - syn
7-- Description: nexys4 target (base; serport loopback, cram protect)
8--
9-- Dependencies: -
10-- To test: tb_nexys4_cram
11-- Target Devices: generic
12-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31
13--
14-- Revision History:
15-- Date Rev Version Comment
16-- 2015-02-01 641 1.1 separate I_BTNRST_N
17-- 2013-09-21 534 1.0 Initial version (derived from nexys3_dummy)
18------------------------------------------------------------------------------
19
20library ieee;
21use ieee.std_logic_1164.all;
22
23use work.slvtypes.all;
24use work.nxcramlib.all;
25
26entity nexys4_cram_dummy is -- NEXYS 4 dummy (base+cram)
27 -- implements nexys4_cram_aif
28 port (
29 I_CLK100 : in slbit; -- 100 MHz board clock
30 I_RXD : in slbit; -- receive data (board view)
31 O_TXD : out slbit; -- transmit data (board view)
32 O_RTS_N : out slbit; -- rx rts (board view; act.low)
33 I_CTS_N : in slbit; -- tx cts (board view; act.low)
34 I_SWI : in slv16; -- n4 switches
35 I_BTN : in slv5; -- n4 buttons
36 I_BTNRST_N : in slbit; -- n4 reset button
37 O_LED : out slv16; -- n4 leds
38 O_RGBLED0 : out slv3; -- n4 rgb-led 0
39 O_RGBLED1 : out slv3; -- n4 rgb-led 1
40 O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
41 O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
42 O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
43 O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
44 O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
45 O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
46 O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
47 O_MEM_CLK : out slbit; -- cram: clock
48 O_MEM_CRE : out slbit; -- cram: command register enable
49 I_MEM_WAIT : in slbit; -- cram: mem wait
50 O_MEM_ADDR : out slv23; -- cram: address lines
51 IO_MEM_DATA : inout slv16 -- cram: data lines
52 );
54
55architecture syn of nexys4_cram_dummy is
56
57begin
58
59 O_TXD <= I_RXD; -- loop back serport
61
62 O_LED <= I_SWI; -- mirror SWI on LED
63
64 O_RGBLED0 <= I_BTN(2 downto 0); -- mirror BTN on RGBLED
65 O_RGBLED1 <= not I_BTNRST_N & I_BTN(4) & I_BTN(3);
66
67 O_ANO_N <= (others=>'1');
68 O_SEG_N <= (others=>'1');
69
70 CRAM : nx_cram_dummy -- connect CRAM to protection dummy
71 port map (
72 O_MEM_CE_N => O_MEM_CE_N,
73 O_MEM_BE_N => O_MEM_BE_N,
74 O_MEM_WE_N => O_MEM_WE_N,
75 O_MEM_OE_N => O_MEM_OE_N,
76 O_MEM_ADV_N => O_MEM_ADV_N,
77 O_MEM_CLK => O_MEM_CLK,
78 O_MEM_CRE => O_MEM_CRE,
79 I_MEM_WAIT => I_MEM_WAIT,
80 O_MEM_ADDR => O_MEM_ADDR,
81 IO_MEM_DATA => IO_MEM_DATA
82 );
83
84end syn;
inout IO_MEM_DATA slv16
std_logic_vector( 22 downto 0) slv23
Definition: slvtypes.vhd:56
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34