w11 - vhd 0.794
W11 CPU core and support modules
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pdp11_hio70.vhd
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1-- $Id: pdp11_hio70.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2015-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: pdp11_hio70 - syn
7-- Description: pdp11: hio led and dsp for sys70
8--
9-- Dependencies: pdp11_statleds
10-- pdp11_ledmux
11-- pdp11_dspmux
12-- Test bench: -
13-- Target Devices: generic
14-- Tool versions: ise 14.7; viv 2014.4-2018.2; ghdl 0.31-0.34
15--
16-- Revision History:
17-- Date Rev Version Comment
18-- 2018-10-07 1054 1.1 use DM_STAT_EXP instead of DM_STAT_DP
19-- 2015-05-01 672 1.0 Initial version (extracted from sys_w11a_*)
20------------------------------------------------------------------------------
21
22library ieee;
23use ieee.std_logic_1164.all;
24use ieee.numeric_std.all;
25
26use work.slvtypes.all;
27use work.pdp11.all;
28
29-- ----------------------------------------------------------------------------
30
31entity pdp11_hio70 is -- hio led and dsp for sys70
32 generic (
33 LWIDTH : positive := 8; -- led width
34 DCWIDTH : positive := 2); -- digit counter width (2 or 3)
35 port (
36 SEL_LED : in slbit; -- led select (0=stat;1=dr)
37 SEL_DSP : in slv2; -- dsp select
38 MEM_ACT_R : in slbit; -- memory active read
39 MEM_ACT_W : in slbit; -- memory active write
40 CP_STAT : in cp_stat_type; -- console port status
41 DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
42 ABCLKDIV : in slv16; -- serport clock divider
43 DISPREG : in slv16; -- display register
44 LED : out slv(LWIDTH-1 downto 0); -- hio leds
45 DSP_DAT : out slv(4*(2**DCWIDTH)-1 downto 0) -- display data
46 );
47end pdp11_hio70;
48
49architecture syn of pdp11_hio70 is
50
51 signal STATLEDS : slv8 := (others=>'0');
52
53begin
54
55 LED_CPU : pdp11_statleds
56 port map (
62 );
63
64 LED_MUX : pdp11_ledmux
65 generic map (
66 LWIDTH => LWIDTH)
67 port map (
68 SEL => SEL_LED,
71 LED => LED
72 );
73
74 DSP_MUX : pdp11_dspmux
75 generic map (
77 port map (
78 SEL => SEL_DSP,
83 );
84
85end syn;
in ABCLKDIV slv16
in SEL slv2
DCWIDTH positive := 2
out DSP_DAT slv( 4*( 2** DCWIDTH)- 1 downto 0)
in DISPREG slv16
in DM_STAT_EXP dm_stat_exp_type
slv8 :=( others => '0') STATLEDS
Definition: pdp11_hio70.vhd:51
in ABCLKDIV slv16
Definition: pdp11_hio70.vhd:42
in CP_STAT cp_stat_type
Definition: pdp11_hio70.vhd:40
DCWIDTH positive := 2
Definition: pdp11_hio70.vhd:34
out DSP_DAT slv( 4*( 2** DCWIDTH)- 1 downto 0)
Definition: pdp11_hio70.vhd:46
in SEL_LED slbit
Definition: pdp11_hio70.vhd:36
in DISPREG slv16
Definition: pdp11_hio70.vhd:43
LWIDTH positive := 8
Definition: pdp11_hio70.vhd:33
in MEM_ACT_W slbit
Definition: pdp11_hio70.vhd:39
out LED slv( LWIDTH- 1 downto 0)
Definition: pdp11_hio70.vhd:44
in MEM_ACT_R slbit
Definition: pdp11_hio70.vhd:38
in SEL_DSP slv2
Definition: pdp11_hio70.vhd:37
in DM_STAT_EXP dm_stat_exp_type
Definition: pdp11_hio70.vhd:41
in STATLEDS slv8
LWIDTH positive := 8
out LED slv( LWIDTH- 1 downto 0)
in DM_STAT_EXP dm_stat_exp_type
in SEL slbit
in CP_STAT cp_stat_type
in MEM_ACT_W slbit
in MEM_ACT_R slbit
out STATLEDS slv8
in DM_STAT_EXP dm_stat_exp_type
Definition: pdp11.vhd:123
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
std_logic_vector slv
Definition: slvtypes.vhd:31