55use ieee.std_logic_1164.
all;
56use ieee.numeric_std.
all;
90 proc_regs :
process (
CLK)
91 variable idat16 : slv16 := (others=>'0');
92 variable idat8 : slv8 := (others=>'0');
93 variable iled : slv4 := (others=>'0');
94 variable irgb_r : slv4 := (others=>'0');
95 variable irgb_g : slv4 := (others=>'0');
96 variable irgb_b : slv4 := (others=>'0');
98 if rising_edge(CLK) then
100 idat16 := (others=>'0');
101 case MODE(1 downto 0) is
104 when "10" => idat16 := DISPREG;
109 if MODE(2) = '0' then
110 idat8 := idat16( 7 downto 0);
112 idat8 := idat16(15 downto 8);
115 iled := (others=>'0');
116 irgb_r := (others=>'0');
117 irgb_g := (others=>'0');
118 irgb_b := (others=>'0');
120 if MODE(3) = '0' then
121 if MODE(2) = '0' then
124 if MODE(0) = '1' then
142 irgb_r(3 downto 0) := CP_STAT.cpurust;
146 if MODE(1) = '1' then
150 irgb_b(0) := not CP_STAT.cpugo;
161 iled := idat8(7 downto 4);
162 irgb_g := idat8(3 downto 0);
171 end process proc_regs;
slv4 :=( others => '0') R_RGB_B
slv4 :=( others => '0') R_RGB_G
slv4 :=( others => '0') R_RGB_R
slv4 :=( others => '0') R_LED
in DM_STAT_EXP dm_stat_exp_type
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 7 downto 0) slv8