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W11 CPU core and support modules
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pdp11_hio70_arty.vhd
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1-- $Id: pdp11_hio70_arty.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2016-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: pdp11_hio70_arty - syn
7-- Description: pdp11: hio led and rgb for sys70 for arty
8--
9-- Dependencies: -
10-- Test bench: -
11-- Target Devices: generic
12-- Tool versions: viv 2015.4-2018.2; ghdl 0.31-0.34
13--
14-- Revision History:
15-- Date Rev Version Comment
16-- 2018-10-07 1054 1.1 use DM_STAT_EXP instead of DM_STAT_DP
17-- 2016-02-27 737 1.0 Initial version
18------------------------------------------------------------------------------
19--
20-- collects the output for LED and RGB leds
21-- MODE = 00xy
22-- LED IO activity
23-- (3) not SER_MONI.txok (shows tx back pressure)
24-- (2) SER_MONI.txact (shows tx activity)
25-- (1) not SER_MONI.rxok (shows rx back pressure)
26-- (0) SER_MONI.rxact (shows rx activity)
27-- RGB_G CPU busy (active cpugo=1, enabled with y=1)
28-- (3) kernel mode, non-wait, pri>0
29-- (2) kernel mode, non-wait, pri=0
30-- (1) supervisor mode
31-- (0) user mode
32-- RGB_R CPU rust (active cpugo=0, enabled with y=1)
33-- (3:0) cpurust code
34-- RGB_B MEM/cmd busy (enabled with x=1)
35-- (3) MEM_ACT_W
36-- (2) MEM_ACT_R
37-- (1) cmdbusy (all rlink access, mostly rdma)
38-- (0) not cpugo
39--
40-- MODE = 0100 (DR emulation)
41-- LED DR(15:12)
42-- RGB_B DR(11:08)
43-- RGB_G DR( 7:04)
44-- RGB_R DR( 3:00)
45--
46-- MODE = 1xyy (show lsb or msb of 16 bit register)
47-- LED show upper, RGB_G lower nibble; x=0 shows lsb and x=1 shows msb
48-- yy = 00: abclkdiv & abclkdiv_f
49-- 01: PC
50-- 10: DISPREG
51-- 11: DR emulation
52--
53
54library ieee;
55use ieee.std_logic_1164.all;
56use ieee.numeric_std.all;
57
58use work.slvtypes.all;
59use work.pdp11.all;
60
61-- ----------------------------------------------------------------------------
62
63entity pdp11_hio70_arty is -- hio led+rgb for sys70 for arty
64 port (
65 CLK : in slbit; -- clock
66 MODE : in slv4; -- mode select
67 MEM_ACT_R : in slbit; -- memory active read
68 MEM_ACT_W : in slbit; -- memory active write
69 CP_STAT : in cp_stat_type; -- console port status
70 DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
71 DISPREG : in slv16; -- display register
72 IOLEDS : in slv4; -- serport ioleds
73 ABCLKDIV : in slv16; -- serport clock divider
74 LED : out slv4; -- hio leds
75 RGB_R : out slv4; -- hio rgb leds - red
76 RGB_G : out slv4; -- hio rgb leds - green
77 RGB_B : out slv4 -- hio rgb leds - blue
78 );
80
81architecture syn of pdp11_hio70_arty is
82
83 signal R_LED : slv4 := (others=>'0');
84 signal R_RGB_R : slv4 := (others=>'0');
85 signal R_RGB_G : slv4 := (others=>'0');
86 signal R_RGB_B : slv4 := (others=>'0');
87
88begin
89
90 proc_regs : process (CLK)
91 variable idat16 : slv16 := (others=>'0');
92 variable idat8 : slv8 := (others=>'0');
93 variable iled : slv4 := (others=>'0');
94 variable irgb_r : slv4 := (others=>'0');
95 variable irgb_g : slv4 := (others=>'0');
96 variable irgb_b : slv4 := (others=>'0');
97 begin
98 if rising_edge(CLK) then
99
100 idat16 := (others=>'0');
101 case MODE(1 downto 0) is
102 when "00" => idat16 := ABCLKDIV;
103 when "01" => idat16 := DM_STAT_EXP.dp_pc;
104 when "10" => idat16 := DISPREG;
105 when "11" => idat16 := DM_STAT_EXP.dp_dsrc;
106 when others => null;
107 end case;
108
109 if MODE(2) = '0' then
110 idat8 := idat16( 7 downto 0);
111 else
112 idat8 := idat16(15 downto 8);
113 end if;
114
115 iled := (others=>'0');
116 irgb_r := (others=>'0');
117 irgb_g := (others=>'0');
118 irgb_b := (others=>'0');
119
120 if MODE(3) = '0' then
121 if MODE(2) = '0' then -- LED shows IO; RGB shows CPU/MEM
122 iled := IOLEDS;
123
124 if MODE(0) = '1' then
125 if CP_STAT.cpugo = '1' then
126 case DM_STAT_EXP.dp_psw.cmode is
127 when c_psw_kmode =>
128 if CP_STAT.cpuwait = '0' then
129 if unsigned(DM_STAT_EXP.dp_psw.pri) = 0 then
130 irgb_g(2) := '1';
131 else
132 irgb_g(3) := '1';
133 end if;
134 end if;
135 when c_psw_smode =>
136 irgb_g(1) := '1';
137 when c_psw_umode =>
138 irgb_g(0) := '1';
139 when others => null;
140 end case;
141 else
142 irgb_r(3 downto 0) := CP_STAT.cpurust;
143 end if;
144 end if; -- MODE(0) = '1'
145
146 if MODE(1) = '1' then
147 irgb_b(3) := MEM_ACT_W;
148 irgb_b(2) := MEM_ACT_R;
149 irgb_b(1) := CP_STAT.cmdbusy;
150 irgb_b(0) := not CP_STAT.cpugo;
151 end if;
152
153 else -- LED+RGB show DR emulation
154 iled := DM_STAT_EXP.dp_dsrc(15 downto 12);
155 irgb_b := DM_STAT_EXP.dp_dsrc(11 downto 8);
156 irgb_g := DM_STAT_EXP.dp_dsrc( 7 downto 4);
157 irgb_r := DM_STAT_EXP.dp_dsrc( 3 downto 0);
158 end if; -- MODE(2) = '0'
159
160 else -- LED+RGB show one of four regs
161 iled := idat8(7 downto 4);
162 irgb_g := idat8(3 downto 0);
163 end if; -- MODE(3) = '0'
164
165 R_LED <= iled;
166 R_RGB_R <= irgb_r;
167 R_RGB_G <= irgb_g;
168 R_RGB_B <= irgb_b;
169 end if;
170
171 end process proc_regs;
172
173 LED <= R_LED;
174 RGB_R <= R_RGB_R;
175 RGB_G <= R_RGB_G;
176 RGB_B <= R_RGB_B;
177
178end syn;
slv4 :=( others => '0') R_RGB_B
slv4 :=( others => '0') R_RGB_G
slv4 :=( others => '0') R_RGB_R
slv4 :=( others => '0') R_LED
in CP_STAT cp_stat_type
in DM_STAT_EXP dm_stat_exp_type
Definition: pdp11.vhd:123
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40