22use ieee.std_logic_1164.
all;
23use ieee.numeric_std.
all;
57 variable ma : slv16 := (others=>'0');
58 variable mb : slv16 := (others=>'0');
59 variable sum : slv16 := (others=>'0');
60 variable nzo : slbit := '0';
66 when c_ounit_asel_dsrc => ma := DSRC;
67 when c_ounit_asel_ddst => ma := DDST;
68 when c_ounit_asel_dtmp => ma := DTMP;
69 when c_ounit_asel_pc => ma := PC;
77 when c_ounit_bsel_ireg6 => mb := "000000000" & IREG8(5 downto 0) & "0";
81 when c_ounit_bsel_vmdout => mb := VMDOUT;
82 when c_ounit_bsel_const => mb := "0000000" & CONST;
87 sum := slv(unsigned(ma) + unsigned(mb));
89 sum := slv(unsigned(ma) - unsigned(mb));
93 if unsigned(sum) = 0 then
std_logic_vector( 8 downto 0) slv9
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 7 downto 0) slv8
std_logic_vector( 1 downto 0) slv2