w11 - vhd 0.794
W11 CPU core and support modules
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s7_cmt_1ce1ce2c.vhd
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1-- $Id: s7_cmt_1ce1ce2c.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: s7_cmt_1ce1ce2c - syn
7-- Description: clocking block for 7-Series: 2 clk+CEs + 2 clk
8--
9-- Dependencies: s7_cmt_sfs
10-- s7_cmt_sfs_2
11-- clkdivce
12-- Test bench: -
13-- Target Devices: generic 7-Series
14-- Tool versions: viv 2017.2; ghdl 0.34
15--
16-- Revision History:
17-- Date Rev Version Comment
18-- 2018-12-16 1086 1.0 Initial version
19------------------------------------------------------------------------------
20
21library ieee;
22use ieee.std_logic_1164.all;
23
24use work.slvtypes.all;
25use work.xlib.all;
26use work.genlib.all;
27
28entity s7_cmt_1ce1ce2c is -- clocking block: 2 clk+CEs; 2 clk
29 generic (
30 CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
31 CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
32 STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
33 CLK0_VCODIV : positive := 1; -- clk0: vco clock divide
34 CLK0_VCOMUL : positive := 1; -- clk0: vco clock multiply
35 CLK0_OUTDIV : positive := 1; -- clk0: output divide
36 CLK0_GENTYPE : string := "PLL"; -- clk0: PLL or MMCM
37 CLK0_CDUWIDTH : positive := 7; -- clk0: usec clock divider width
38 CLK0_USECDIV : positive := 50; -- clk0: divider ratio for usec pulse
39 CLK0_MSECDIV : positive := 1000; -- clk0: divider ratio for msec pulse
40 CLK1_VCODIV : positive := 1; -- clk1: vco clock divide
41 CLK1_VCOMUL : positive := 1; -- clk1: vco clock multiply
42 CLK1_OUTDIV : positive := 1; -- clk1: output divide
43 CLK1_GENTYPE : string := "MMCM"; -- clk1: PLL or MMCM
44 CLK1_CDUWIDTH : positive := 7; -- clk1: usec clock divider width
45 CLK1_USECDIV : positive := 50; -- clk1: divider ratio for usec pulse
46 CLK1_MSECDIV : positive := 1000; -- clk1: divider ratio for msec pulse
47 CLK23_VCODIV : positive := 1; -- clk2+3: vco clock divide
48 CLK23_VCOMUL : positive := 1; -- clk2+3: vco clock multiply
49 CLK2_OUTDIV : positive := 1; -- clk2: output divide
50 CLK3_OUTDIV : positive := 1; -- clk3: output divide
51 CLK23_GENTYPE : string := "PLL"); -- clk2+3: PLL or MMCM
52 port (
53 CLKIN : in slbit; -- clock input
54 CLK0 : out slbit; -- clk0: clock output
55 CE0_USEC : out slbit; -- clk0: usec pulse
56 CE0_MSEC : out slbit; -- clk0: msec pulse
57 CLK1 : out slbit; -- clk1: clock output
58 CE1_USEC : out slbit; -- clk1: usec pulse
59 CE1_MSEC : out slbit; -- clk1: msec pulse
60 CLK2 : out slbit; -- clk2: clock output
61 CLK3 : out slbit; -- clk3: clock output
62 LOCKED : out slbit -- all PLL/MMCM locked
63 );
65
66architecture syn of s7_cmt_1ce1ce2c is
67
68 signal CLK0_L : slbit := '0';
69 signal CLK1_L : slbit := '0';
70 signal LOCKED0 : slbit := '0';
71 signal LOCKED1 : slbit := '0';
72 signal LOCKED23 : slbit := '0';
73
74begin
75
76 GEN_CLK0 : s7_cmt_sfs -- clock generator 0 -----------------
77 generic map (
78 VCO_DIVIDE => CLK0_VCODIV,
79 VCO_MULTIPLY => CLK0_VCOMUL,
80 OUT_DIVIDE => CLK0_OUTDIV,
81 CLKIN_PERIOD => CLKIN_PERIOD,
82 CLKIN_JITTER => CLKIN_JITTER,
83 STARTUP_WAIT => STARTUP_WAIT,
84 GEN_TYPE => CLK0_GENTYPE)
85 port map (
86 CLKIN => CLKIN,
87 CLKFX => CLK0_L,
88 LOCKED => LOCKED0
89 );
90
91 DIV_CLK0 : clkdivce -- usec/msec clock divider 0 ---------
92 generic map (
93 CDUWIDTH => CLK0_CDUWIDTH,
94 USECDIV => CLK0_USECDIV,
95 MSECDIV => CLK0_MSECDIV)
96 port map (
97 CLK => CLK0_L,
98 CE_USEC => CE0_USEC,
99 CE_MSEC => CE0_MSEC
100 );
101
102 GEN_CLK1 : s7_cmt_sfs -- clock generator 1 -----------------
103 generic map (
104 VCO_DIVIDE => CLK1_VCODIV,
105 VCO_MULTIPLY => CLK1_VCOMUL,
106 OUT_DIVIDE => CLK1_OUTDIV,
107 CLKIN_PERIOD => CLKIN_PERIOD,
108 CLKIN_JITTER => CLKIN_JITTER,
109 STARTUP_WAIT => STARTUP_WAIT,
110 GEN_TYPE => CLK1_GENTYPE)
111 port map (
112 CLKIN => CLKIN,
113 CLKFX => CLK1_L,
114 LOCKED => LOCKED1
115 );
116
117 DIV_CLK1 : clkdivce -- usec/msec clock divider 1 ---------
118 generic map (
119 CDUWIDTH => CLK1_CDUWIDTH,
120 USECDIV => CLK1_USECDIV,
121 MSECDIV => CLK1_MSECDIV)
122 port map (
123 CLK => CLK1_L,
124 CE_USEC => CE1_USEC,
125 CE_MSEC => CE1_MSEC
126 );
127
128 GEN_CLK23 : s7_cmt_sfs_2 -- clock generator 2+3 ---------------
129 generic map (
130 VCO_DIVIDE => CLK23_VCODIV,
131 VCO_MULTIPLY => CLK23_VCOMUL,
132 OUT0_DIVIDE => CLK2_OUTDIV,
133 OUT1_DIVIDE => CLK3_OUTDIV,
134 CLKIN_PERIOD => CLKIN_PERIOD,
135 CLKIN_JITTER => CLKIN_JITTER,
136 STARTUP_WAIT => STARTUP_WAIT,
137 GEN_TYPE => CLK23_GENTYPE)
138 port map (
139 CLKIN => CLKIN,
140 CLKOUT0 => CLK2,
141 CLKOUT1 => CLK3,
142 LOCKED => LOCKED23
143 );
144
145 CLK0 <= CLK0_L;
146 CLK1 <= CLK1_L;
147 LOCKED <= LOCKED0 and LOCKED1 and LOCKED23;
148
149end syn;
CLK1_GENTYPE string := "MMCM"
CLK0_VCODIV positive := 1
CLKIN_PERIOD real := 10.0
out CE0_MSEC slbit
CLK1_MSECDIV positive := 1000
CLK0_CDUWIDTH positive := 7
CLK2_OUTDIV positive := 1
CLK1_VCOMUL positive := 1
CLK1_VCODIV positive := 1
out CE0_USEC slbit
CLK23_VCODIV positive := 1
CLK0_MSECDIV positive := 1000
CLK1_CDUWIDTH positive := 7
CLKIN_JITTER real := 0.01
STARTUP_WAIT boolean := false
out CE1_USEC slbit
CLK0_USECDIV positive := 50
CLK23_GENTYPE string := "PLL"
out CE1_MSEC slbit
CLK0_OUTDIV positive := 1
CLK23_VCOMUL positive := 1
CLK0_GENTYPE string := "PLL"
CLK1_OUTDIV positive := 1
CLK0_VCOMUL positive := 1
CLK1_USECDIV positive := 50
CLK3_OUTDIV positive := 1
std_logic slbit
Definition: slvtypes.vhd:30
Definition: xlib.vhd:35