22use ieee.std_logic_1164.
all;
76 GEN_CLK0 :
s7_cmt_sfs -- clock generator
0 -----------------
91 DIV_CLK0 :
clkdivce -- usec/msec clock divider
0 ---------
102 GEN_CLK1 :
s7_cmt_sfs -- clock generator
1 -----------------
117 DIV_CLK1 :
clkdivce -- usec/msec clock divider
1 ---------
128 GEN_CLK23 :
s7_cmt_sfs_2 -- clock generator
2+3 ---------------
CLK1_GENTYPE string := "MMCM"
CLK0_VCODIV positive := 1
CLKIN_PERIOD real := 10.0
CLK1_MSECDIV positive := 1000
CLK0_CDUWIDTH positive := 7
CLK2_OUTDIV positive := 1
CLK1_VCOMUL positive := 1
CLK1_VCODIV positive := 1
CLK23_VCODIV positive := 1
CLK0_MSECDIV positive := 1000
CLK1_CDUWIDTH positive := 7
CLKIN_JITTER real := 0.01
STARTUP_WAIT boolean := false
CLK0_USECDIV positive := 50
CLK23_GENTYPE string := "PLL"
CLK0_OUTDIV positive := 1
CLK23_VCOMUL positive := 1
CLK0_GENTYPE string := "PLL"
CLK1_OUTDIV positive := 1
CLK0_VCOMUL positive := 1
CLK1_USECDIV positive := 50
CLK3_OUTDIV positive := 1