28use ieee.std_logic_1164.
all;
46component cnt_array_dram
is
48 AWIDTH :
positive :=
4;
49 DWIDTH :
positive :=
16);
52 RESET :
in slbit := '
0';
53 CE :
in slv(
2**AWIDTH
-1 downto 0);
54 ADDR :
out slv(AWIDTH
-1 downto 0);
55 DATA :
out slv(DWIDTH
-1 downto 0);
60component cnt_array_regs
is
62 AWIDTH :
positive :=
4;
63 DWIDTH :
positive :=
16);
66 RESET :
in slbit := '
0';
67 CE :
in slv(
2**AWIDTH
-1 downto 0);
68 ADDR :
in slv(AWIDTH
-1 downto 0);
69 DATA :
out slv(DWIDTH
-1 downto 0)
76 CEDIV :
positive :=
3;
116component gray_cnt_6
is
119 RESET :
in slbit := '
0';
120 CE :
in slbit := '
1';
147 TWIDTH :
positive :=
4;
148 RETRIG :
boolean := true);
151 CE :
in slbit := '
1';
152 DELAY :
in slv(TWIDTH
-1 downto 0) := (
others=>'
1');
154 STOP :
in slbit := '
0';
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)
out DATA slv( DWIDTH- 1 downto 0)
out DATA slv( DWIDTH- 1 downto 0)
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 4 downto 0) slv5