w11 - vhd 0.794
W11 CPU core and support modules
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genlib.vhd
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1-- $Id: genlib.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Package Name: genlib
7-- Description: some general purpose components
8--
9-- Dependencies: -
10-- Tool versions: ise 8.1-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33
11-- Revision History:
12-- Date Rev Version Comment
13-- 2016-04-02 757 1.1 move cdc_pulse to cdclib
14-- 2016-03-25 751 1.0.10 add gray_cnt_6
15-- 2012-12-29 466 1.0.9 add led_pulse_stretch
16-- 2011-11-09 421 1.0.8 add cdc_pulse
17-- 2010-04-17 277 1.0.7 timer: no default for START,DONE,BUSY; drop STOP
18-- 2010-04-02 273 1.0.6 add timer
19-- 2008-01-20 112 1.0.5 rename clkgen->clkdivce
20-- 2007-12-26 106 1.0.4 added gray_cnt_(4|5|n|gen) and gray2bin_gen
21-- 2007-12-25 105 1.0.3 RESET:='0' defaults
22-- 2007-06-17 58 1.0.2 added debounce_gen
23-- 2007-06-16 57 1.0.1 added cnt_array_dram, cnt_array_regs
24-- 2007-06-03 45 1.0 Initial version
25------------------------------------------------------------------------------
26
27library ieee;
28use ieee.std_logic_1164.all;
29
30use work.slvtypes.all;
31
32package genlib is
33
34component clkdivce is -- generate usec/msec ce pulses
35 generic (
36 CDUWIDTH : positive := 6; -- usec clock divider width
37 USECDIV : positive := 50; -- divider ratio for usec pulse
38 MSECDIV : positive := 1000); -- divider ratio for msec pulse
39 port (
40 CLK : in slbit; -- input clock
41 CE_USEC : out slbit; -- usec pulse
42 CE_MSEC : out slbit -- msec pulse
43 );
44end component;
45
46component cnt_array_dram is -- counter array, dram based
47 generic (
48 AWIDTH : positive := 4; -- address width
49 DWIDTH : positive := 16); -- data width
50 port (
51 CLK : in slbit; -- clock
52 RESET : in slbit := '0'; -- clear counters
53 CE : in slv(2**AWIDTH-1 downto 0); -- count enables
54 ADDR : out slv(AWIDTH-1 downto 0); -- counter address
55 DATA : out slv(DWIDTH-1 downto 0); -- counter data
56 ACT : out slbit -- active (not reseting)
57 );
58end component;
59
60component cnt_array_regs is -- counter array, register based
61 generic (
62 AWIDTH : positive := 4; -- address width
63 DWIDTH : positive := 16); -- data width
64 port (
65 CLK : in slbit; -- clock
66 RESET : in slbit := '0'; -- clear counters
67 CE : in slv(2**AWIDTH-1 downto 0); -- count enables
68 ADDR : in slv(AWIDTH-1 downto 0); -- address
69 DATA : out slv(DWIDTH-1 downto 0) -- counter data
70 );
71end component;
72
73component debounce_gen is -- debounce, generic vector
74 generic (
75 CWIDTH : positive := 2; -- clock interval counter width
76 CEDIV : positive := 3; -- clock interval divider
77 DWIDTH : positive := 8); -- data width
78 port (
79 CLK : in slbit; -- clock
80 RESET : in slbit := '0'; -- reset
81 CE_INT : in slbit; -- clock interval enable (usec or msec)
82 DI : in slv(DWIDTH-1 downto 0); -- data in
83 DO : out slv(DWIDTH-1 downto 0) -- data out
84 );
85end component;
86
87component gray_cnt_gen is -- gray code counter, generic vector
88 generic (
89 DWIDTH : positive := 4); -- data width
90 port (
91 CLK : in slbit; -- clock
92 RESET : in slbit := '0'; -- reset
93 CE : in slbit := '1'; -- count enable
94 DATA : out slv(DWIDTH-1 downto 0) -- data out
95 );
96end component;
97
98component gray_cnt_4 is -- 4 bit gray code counter (ROM based)
99 port (
100 CLK : in slbit; -- clock
101 RESET : in slbit := '0'; -- reset
102 CE : in slbit := '1'; -- count enable
103 DATA : out slv4 -- data out
104 );
105end component;
106
107component gray_cnt_5 is -- 5 bit gray code counter (ROM based)
108 port (
109 CLK : in slbit; -- clock
110 RESET : in slbit := '0'; -- reset
111 CE : in slbit := '1'; -- count enable
112 DATA : out slv5 -- data out
113 );
114end component;
115
116component gray_cnt_6 is -- 6 bit gray code counter (ROM based)
117 port (
118 CLK : in slbit; -- clock
119 RESET : in slbit := '0'; -- reset
120 CE : in slbit := '1'; -- count enable
121 DATA : out slv5 -- data out
122 );
123end component;
124
125component gray_cnt_n is -- n bit gray code counter
126 generic (
127 DWIDTH : positive := 8); -- data width
128 port (
129 CLK : in slbit; -- clock
130 RESET : in slbit := '0'; -- reset
131 CE : in slbit := '1'; -- count enable
132 DATA : out slv(DWIDTH-1 downto 0) -- data out
133 );
134end component;
135
136component gray2bin_gen is -- gray->bin converter, generic vector
137 generic (
138 DWIDTH : positive := 4); -- data width
139 port (
140 DI : in slv(DWIDTH-1 downto 0); -- gray code input
141 DO : out slv(DWIDTH-1 downto 0) -- binary code output
142 );
143end component;
144
145component timer is -- retriggerable timer
146 generic (
147 TWIDTH : positive := 4; -- timer counter width
148 RETRIG : boolean := true); -- re-triggerable true/false
149 port (
150 CLK : in slbit; -- clock
151 CE : in slbit := '1'; -- clock enable
152 DELAY : in slv(TWIDTH-1 downto 0) := (others=>'1'); -- timer delay
153 START : in slbit; -- start timer
154 STOP : in slbit := '0'; -- stop timer
155 DONE : out slbit; -- mark last delay cycle
156 BUSY : out slbit -- timer running
157 );
158end component;
159
160component led_pulse_stretch is -- pulse stretcher for leds
161 port (
162 CLK : in slbit; -- clock
163 CE_INT : in slbit; -- pulse time unit clock enable
164 RESET : in slbit := '0'; -- reset
165 DIN : in slbit; -- data in
166 POUT : out slbit -- pulse out
167 );
168end component;
169
170end package genlib;
out CE_MSEC slbit
Definition: clkdivce.vhd:39
USECDIV positive := 50
Definition: clkdivce.vhd:33
CDUWIDTH positive := 6
Definition: clkdivce.vhd:32
out CE_USEC slbit
Definition: clkdivce.vhd:37
MSECDIV positive := 1000
Definition: clkdivce.vhd:34
in CLK slbit
Definition: clkdivce.vhd:36
DWIDTH positive := 8
in CE_INT slbit
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)
CWIDTH positive := 2
in CLK slbit
CEDIV positive := 3
in RESET slbit := '0'
DWIDTH positive := 4
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)
in CE slbit := '1'
Definition: gray_cnt_4.vhd:33
out DATA slv4
Definition: gray_cnt_4.vhd:35
in CLK slbit
Definition: gray_cnt_4.vhd:31
in RESET slbit := '0'
Definition: gray_cnt_4.vhd:32
in CE slbit := '1'
Definition: gray_cnt_5.vhd:33
out DATA slv5
Definition: gray_cnt_5.vhd:35
in CLK slbit
Definition: gray_cnt_5.vhd:31
in RESET slbit := '0'
Definition: gray_cnt_5.vhd:32
in CE slbit := '1'
DWIDTH positive := 4
in CLK slbit
out DATA slv( DWIDTH- 1 downto 0)
in RESET slbit := '0'
DWIDTH positive := 8
Definition: gray_cnt_n.vhd:44
in CE slbit := '1'
Definition: gray_cnt_n.vhd:48
in CLK slbit
Definition: gray_cnt_n.vhd:46
out DATA slv( DWIDTH- 1 downto 0)
Definition: gray_cnt_n.vhd:50
in RESET slbit := '0'
Definition: gray_cnt_n.vhd:47
in RESET slbit := '0'
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector slv
Definition: slvtypes.vhd:31