w11 - vhd 0.794
W11 CPU core and support modules
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s7_cmt_1ce1ce.vhd
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1-- $Id: s7_cmt_1ce1ce.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: s7_cmt_1ce1ce - syn
7-- Description: clocking block for 7-Series: 2 clk with CEs
8--
9-- Dependencies: s7_cmt_sfs
10-- clkdivce
11-- Test bench: -
12-- Target Devices: generic 7-Series
13-- Tool versions: viv 2017.2; ghdl 0.34
14--
15-- Revision History:
16-- Date Rev Version Comment
17-- 2018-12-16 1086 1.0 Initial version
18------------------------------------------------------------------------------
19
20library ieee;
21use ieee.std_logic_1164.all;
22
23use work.slvtypes.all;
24use work.xlib.all;
25use work.genlib.all;
26
27entity s7_cmt_1ce1ce is -- clocking block: 2 clk with CEs
28 generic (
29 CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
30 CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
31 STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
32 CLK0_VCODIV : positive := 1; -- clk0: vco clock divide
33 CLK0_VCOMUL : positive := 1; -- clk0: vco clock multiply
34 CLK0_OUTDIV : positive := 1; -- clk0: output divide
35 CLK0_GENTYPE : string := "PLL"; -- clk0: PLL or MMCM
36 CLK0_CDUWIDTH : positive := 7; -- clk0: usec clock divider width
37 CLK0_USECDIV : positive := 50; -- clk0: divider ratio for usec pulse
38 CLK0_MSECDIV : positive := 1000; -- clk0: divider ratio for msec pulse
39 CLK1_VCODIV : positive := 1; -- clk1: vco clock divide
40 CLK1_VCOMUL : positive := 1; -- clk1: vco clock multiply
41 CLK1_OUTDIV : positive := 1; -- clk1: output divide
42 CLK1_GENTYPE : string := "MMCM"; -- clk1: PLL or MMCM
43 CLK1_CDUWIDTH : positive := 7; -- clk1: usec clock divider width
44 CLK1_USECDIV : positive := 50; -- clk1: divider ratio for usec pulse
45 CLK1_MSECDIV : positive := 1000); -- clk1: divider ratio for msec pulse
46 port (
47 CLKIN : in slbit; -- clock input
48 CLK0 : out slbit; -- clk0: clock output
49 CE0_USEC : out slbit; -- clk0: usec pulse
50 CE0_MSEC : out slbit; -- clk0: msec pulse
51 CLK1 : out slbit; -- clk1: clock output
52 CE1_USEC : out slbit; -- clk1: usec pulse
53 CE1_MSEC : out slbit; -- clk1: msec pulse
54 LOCKED : out slbit -- all PLL/MMCM locked
55 );
57
58architecture syn of s7_cmt_1ce1ce is
59
60 signal CLK0_L : slbit := '0';
61 signal CLK1_L : slbit := '0';
62 signal LOCKED0 : slbit := '0';
63 signal LOCKED1 : slbit := '0';
64
65begin
66
67 GEN_CLK0 : s7_cmt_sfs -- clock generator 0 -----------------
68 generic map (
69 VCO_DIVIDE => CLK0_VCODIV,
70 VCO_MULTIPLY => CLK0_VCOMUL,
71 OUT_DIVIDE => CLK0_OUTDIV,
72 CLKIN_PERIOD => CLKIN_PERIOD,
73 CLKIN_JITTER => CLKIN_JITTER,
74 STARTUP_WAIT => STARTUP_WAIT,
75 GEN_TYPE => CLK0_GENTYPE)
76 port map (
77 CLKIN => CLKIN,
78 CLKFX => CLK0_L,
79 LOCKED => LOCKED0
80 );
81
82 DIV_CLK0 : clkdivce -- usec/msec clock divider 0 ---------
83 generic map (
84 CDUWIDTH => CLK0_CDUWIDTH,
85 USECDIV => CLK0_USECDIV,
86 MSECDIV => CLK0_MSECDIV)
87 port map (
88 CLK => CLK0_L,
89 CE_USEC => CE0_USEC,
90 CE_MSEC => CE0_MSEC
91 );
92
93 GEN_CLK1 : s7_cmt_sfs -- clock generator serport -----------
94 generic map (
95 VCO_DIVIDE => CLK1_VCODIV,
96 VCO_MULTIPLY => CLK1_VCOMUL,
97 OUT_DIVIDE => CLK1_OUTDIV,
98 CLKIN_PERIOD => CLKIN_PERIOD,
99 CLKIN_JITTER => CLKIN_JITTER,
100 STARTUP_WAIT => STARTUP_WAIT,
101 GEN_TYPE => CLK1_GENTYPE)
102 port map (
103 CLKIN => CLKIN,
104 CLKFX => CLK1_L,
105 LOCKED => LOCKED1
106 );
107
108 DIV_CLK1 : clkdivce -- usec/msec clock divider 1 ---------
109 generic map (
110 CDUWIDTH => CLK1_CDUWIDTH,
111 USECDIV => CLK1_USECDIV,
112 MSECDIV => CLK1_MSECDIV)
113 port map (
114 CLK => CLK1_L,
115 CE_USEC => CE1_USEC,
116 CE_MSEC => CE1_MSEC
117 );
118
119 CLK0 <= CLK0_L;
120 CLK1 <= CLK1_L;
121 LOCKED <= LOCKED0 and LOCKED1;
122
123end syn;
slbit := '0' CLK1_L
slbit := '0' CLK0_L
slbit := '0' LOCKED1
slbit := '0' LOCKED0
CLK1_GENTYPE string := "MMCM"
CLK0_VCODIV positive := 1
CLKIN_PERIOD real := 10.0
out CE0_MSEC slbit
CLK1_MSECDIV positive := 1000
CLK0_CDUWIDTH positive := 7
in CLKIN slbit
CLK1_VCOMUL positive := 1
CLK1_VCODIV positive := 1
out CE0_USEC slbit
out CLK0 slbit
CLK0_MSECDIV positive := 1000
CLK1_CDUWIDTH positive := 7
out CLK1 slbit
CLKIN_JITTER real := 0.01
STARTUP_WAIT boolean := false
out CE1_USEC slbit
CLK0_USECDIV positive := 50
out CE1_MSEC slbit
CLK0_OUTDIV positive := 1
out LOCKED slbit
CLK0_GENTYPE string := "PLL"
CLK1_OUTDIV positive := 1
CLK0_VCOMUL positive := 1
CLK1_USECDIV positive := 50
std_logic slbit
Definition: slvtypes.vhd:30
Definition: xlib.vhd:35