28use ieee.std_logic_1164.
all;
29use ieee.numeric_std.
all;
92 report "assert(CDINIT <= 2**CDWIDTH-1): CDINIT too large for given CDWIDTH"
95 proc_regs:
process (
CLK)
98 if rising_edge(CLK) then
106 end process proc_regs;
113 variable iact : slbit := '0';
114 variable idone : slbit := '0';
128 if r.seen1 = '0' then
129 n.mcnt := slv(unsigned(r.mcnt) + 1);
138 n.seen1 := r.seen1 or RXSD;
157 n.ccnt := slv(unsigned(n.ccnt) + 1);
170 end process proc_next;
(s_idle,s_break,s_wait,s_sync) state_type
slv( CDWIDTH- 1+ 3 downto 0) := slv( to_unsigned( 2**( CDWIDTH+ 3)- 3, CDWIDTH+ 3) ) ccntinit
slv7 :=( others => '0') mcntzero
regs_type :=( slv( to_unsigned( CDINIT, CDWIDTH) )& "000",( others => '0'), '0', s_idle) regs_init
regs_type := regs_init R_REGS
slv7 :=( others => '1') mcntlast
out CLKDIV slv( CDWIDTH- 1 downto 0)
std_logic_vector( 6 downto 0) slv7
std_logic_vector( 2 downto 0) slv3