41use ieee.std_logic_1164.
all;
42use ieee.numeric_std.
all;
97 proc_regs:
process (
CLK)
100 if rising_edge(CLK) then
104 end process proc_regs;
111 variable dbit : slbit := '0';
112 variable ld_ccnt : slbit := '0';
113 variable tc_ccnt : slbit := '0';
114 variable tc_bcnt : slbit := '0';
115 variable ld_dcnt : slbit := '0';
116 variable ld_bcnt : slbit := '0';
117 variable ce_bcnt : slbit := '0';
118 variable iact : slbit := '0';
119 variable ival : slbit := '0';
120 variable ierr : slbit := '0';
138 if unsigned(r.ccnt) = 0 then
141 if unsigned(r.bcnt) = 9 then
145 if unsigned(r.dcnt) > unsigned("00" & CLKDIV(CDWIDTH-1 downto 1)) then
155 if tc_ccnt = '1' then
168 if tc_ccnt = '1' then
173 if dbit='1' and RXSD='1' then
188 if tc_ccnt = '1' then
198 if tc_ccnt = '1' then
206 n.sreg := dbit & r.sreg(7 downto 1);
207 if tc_ccnt = '1' then
208 if tc_bcnt = '1' then
217 if tc_bcnt = '1' then
225 if tc_ccnt = '1' then
230 if dbit='1' and RXSD='1' then
251 if tc_ccnt = '1' then
271 if ld_ccnt = '1' then
274 n.ccnt := slv(unsigned(r.ccnt) - 1);
277 if ld_dcnt = '1' then
278 n.dcnt(CDWIDTH downto 1) := (others=>'0');
282 n.dcnt := slv(unsigned(r.dcnt) + 1);
286 if ld_bcnt = '1' then
287 n.bcnt := (others=>'0');
289 if ce_bcnt = '1' then
290 n.bcnt := slv(unsigned(r.bcnt) + 1);
301 end process proc_next;
slv( CDWIDTH downto 0) :=( others => '0') dcntzero
regs_type := regs_init R_REGS
(s_idle,s_colb0,s_endb0,s_colbx,s_endbx,s_colb9,s_endb9) state_type
regs_type :=( s_idle, ccntzero, dcntzero,( others => '0'),( others => '0')) regs_init
slv( CDWIDTH- 1 downto 0) :=( others => '0') ccntzero
in CLKDIV slv( CDWIDTH- 1 downto 0)
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 7 downto 0) slv8