26use ieee.std_logic_1164.
all;
27use ieee.numeric_std.
all;
68 proc_regs:
process (
CLK)
71 if rising_edge(CLK) then
75 end process proc_regs;
81 variable ld_ccnt : slbit := '0';
91 n.bcnt := (others=>'0');
99 if unsigned(r.ccnt) = 0 then
101 n.sreg := '1' & r.sreg(8 downto 1);
102 n.bcnt := slv(unsigned(r.bcnt) + 1);
103 if unsigned(r.bcnt) = 9 then
114 if ld_ccnt = '1' then
117 n.ccnt := slv(unsigned(r.ccnt) - 1);
125 end process proc_next;
regs_type :=( cntzero,( others => '0'),( others => '1'), '0') regs_init
regs_type := regs_init N_REGS
regs_type := regs_init R_REGS
slv( CDWIDTH- 1 downto 0) :=( others => '0') cntzero
in CLKDIV slv( CDWIDTH- 1 downto 0)
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 8 downto 0) slv9
std_logic_vector( 7 downto 0) slv8