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W11 CPU core and support modules
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serport_uart_tx.vhd
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1-- $Id: serport_uart_tx.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: serport_uart_tx - syn
7-- Description: serial port UART - transmitter
8--
9-- Dependencies: -
10-- Test bench: tb/tb_serport_uart_rxtx
11-- Target Devices: generic
12-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.2; ghdl 0.18-0.33
13-- Revision History:
14-- Date Rev Version Comment
15-- 2011-10-22 417 1.0.4 now numeric_std clean
16-- 2007-10-21 91 1.0.3 use 1 stop bits (redesigned _rx allows this)
17-- 2007-10-19 90 1.0.2 use 2 stop bits (allow CLKDIV=0 operation in sim)
18-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
19-- 2007-06-30 62 1.0 Initial version
20------------------------------------------------------------------------------
21-- NOTE: for test bench usage a copy of all serport_* entities, with _tb
22-- !!!! appended to the name, has been created in the /tb sub folder.
23-- !!!! Ensure to update the copy when this file is changed !!
24
25library ieee;
26use ieee.std_logic_1164.all;
27use ieee.numeric_std.all;
28
29use work.slvtypes.all;
30
31entity serport_uart_tx is -- serial port uart: transmit part
32 generic (
33 CDWIDTH : positive := 13); -- clk divider width
34 port (
35 CLK : in slbit; -- clock
36 RESET : in slbit; -- reset
37 CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
38 TXSD : out slbit; -- transmit serial data (uart view)
39 TXDATA : in slv8; -- transmit data in
40 TXENA : in slbit; -- transmit data enable
41 TXBUSY : out slbit -- transmit busy
42 );
44
45
46architecture syn of serport_uart_tx is
47
48 type regs_type is record
49 ccnt : slv(CDWIDTH-1 downto 0); -- clock divider counter
50 bcnt : slv4; -- bit counter
51 sreg : slv9; -- output shift register
52 busy : slbit;
53 end record regs_type;
54
55 constant cntzero : slv(CDWIDTH-1 downto 0) := (others=>'0');
56 constant regs_init : regs_type := (
57 cntzero,
58 (others=>'0'),
59 (others=>'1'), -- sreg to all 1 !!
60 '0'
61 );
62
63 signal R_REGS : regs_type := regs_init; -- state registers
64 signal N_REGS : regs_type := regs_init; -- next value state regs
65
66begin
67
68 proc_regs: process (CLK)
69 begin
70
71 if rising_edge(CLK) then
72 R_REGS <= N_REGS;
73 end if;
74
75 end process proc_regs;
76
77 proc_next: process (R_REGS, RESET, CLKDIV, TXDATA, TXENA)
78
79 variable r : regs_type := regs_init;
80 variable n : regs_type := regs_init;
81 variable ld_ccnt : slbit := '0';
82
83 begin
84
85 r := R_REGS;
86 n := R_REGS;
87 ld_ccnt := '0';
88
89 if r.busy = '0' then
90 ld_ccnt := '1';
91 n.bcnt := (others=>'0');
92 if TXENA = '1' then
93 n.sreg := TXDATA & '0'; -- add start (0) bit
94 n.busy := '1';
95 end if;
96
97 else
98
99 if unsigned(r.ccnt) = 0 then
100 ld_ccnt := '1';
101 n.sreg := '1' & r.sreg(8 downto 1);
102 n.bcnt := slv(unsigned(r.bcnt) + 1);
103 if unsigned(r.bcnt) = 9 then -- if 10 bits send
104 n.busy := '0'; -- declare all done
105 end if;
106 end if;
107 end if;
108
109 if RESET = '1' then
110 ld_ccnt := '1';
111 n.busy := '0';
112 end if;
113
114 if ld_ccnt = '1' then
115 n.ccnt := CLKDIV;
116 else
117 n.ccnt := slv(unsigned(r.ccnt) - 1);
118 end if;
119
120 N_REGS <= n;
121
122 TXBUSY <= r.busy;
123 TXSD <= r.sreg(0);
124
125 end process proc_next;
126
127end syn;
regs_type :=( cntzero,( others => '0'),( others => '1'), '0') regs_init
regs_type := regs_init N_REGS
regs_type := regs_init R_REGS
slv( CDWIDTH- 1 downto 0) :=( others => '0') cntzero
CDWIDTH positive := 13
in CLKDIV slv( CDWIDTH- 1 downto 0)
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 8 downto 0) slv9
Definition: slvtypes.vhd:41
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector slv
Definition: slvtypes.vhd:31