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W11 CPU core and support modules
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simclkcnt.vhd
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-- $Id: simclkcnt.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: simclkcnt - sim
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-- Description: test bench system clock cycle counter
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: xst 12.1-14.7; viv 2016.2; ghdl 0.29-0.33
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-12-23 444 2.0 CLK_CYCLE now an integer
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-- 2011-11-12 423 1.0.1 now numeric_std clean
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-- 2010-11-13 72 1.0 Initial version
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------------------------------------------------------------------------------
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library
ieee
;
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use
ieee.std_logic_1164.
all
;
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use
work.
slvtypes
.
all
;
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entity
simclkcnt
is
-- test bench system clock cycle counter
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port
(
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CLK
:
in
slbit
;
-- clock
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CLK_CYCLE
:
out
integer
-- clock cycle number
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)
;
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end
entity
simclkcnt
;
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architecture
sim
of
simclkcnt
is
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signal
R_CLKCNT
:
integer
:=
0
;
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begin
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proc_clk:
process
(
CLK
)
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begin
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if
rising_edge
(
CLK
)
then
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R_CLKCNT
<=
R_CLKCNT
+
1
;
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end
if
;
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end
process
proc_clk
;
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CLK_CYCLE
<=
R_CLKCNT
;
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end
sim;
simclkcnt.sim
Definition:
simclkcnt.vhd:32
simclkcnt.sim.R_CLKCNT
integer := 0 R_CLKCNT
Definition:
simclkcnt.vhd:33
simclkcnt
Definition:
simclkcnt.vhd:25
simclkcnt.CLK_CYCLE
out CLK_CYCLE integer
Definition:
simclkcnt.vhd:29
simclkcnt.CLK
in CLK slbit
Definition:
simclkcnt.vhd:27
slvtypes
Definition:
slvtypes.vhd:28
slvtypes.slbit
std_logic slbit
Definition:
slvtypes.vhd:30
vlib
simlib
simclkcnt.vhd
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