w11 - vhd 0.794
W11 CPU core and support modules
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simclkcnt.vhd
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1-- $Id: simclkcnt.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: simclkcnt - sim
7-- Description: test bench system clock cycle counter
8--
9-- Dependencies: -
10-- Test bench: -
11-- Target Devices: generic
12-- Tool versions: xst 12.1-14.7; viv 2016.2; ghdl 0.29-0.33
13--
14-- Revision History:
15-- Date Rev Version Comment
16-- 2011-12-23 444 2.0 CLK_CYCLE now an integer
17-- 2011-11-12 423 1.0.1 now numeric_std clean
18-- 2010-11-13 72 1.0 Initial version
19------------------------------------------------------------------------------
20
21library ieee;
22use ieee.std_logic_1164.all;
23use work.slvtypes.all;
24
25entity simclkcnt is -- test bench system clock cycle counter
26 port (
27 CLK : in slbit; -- clock
28 CLK_CYCLE : out integer -- clock cycle number
29 );
30end entity simclkcnt;
31
32architecture sim of simclkcnt is
33 signal R_CLKCNT : integer := 0;
34begin
35
36 proc_clk: process (CLK)
37 begin
38
39 if rising_edge(CLK) then
40 R_CLKCNT <= R_CLKCNT + 1;
41 end if;
42
43 end process proc_clk;
44
46
47end sim;
integer := 0 R_CLKCNT
Definition: simclkcnt.vhd:33
out CLK_CYCLE integer
Definition: simclkcnt.vhd:29
in CLK slbit
Definition: simclkcnt.vhd:27
std_logic slbit
Definition: slvtypes.vhd:30