35use ieee.std_logic_1164.
all;
36use ieee.numeric_std.
all;
93 report "assert(DCWIDTH=2 or DCWIDTH=3): unsupported DCWIDTH"
97 report "assert(CDWIDTH >= 5): CDWIDTH too small"
103 if rising_edge(CLK) then
107 end process proc_regs;
114 variable cano : slv((2**DCWIDTH)-1 downto 0) := (others=>'0');
121 n.cdiv := slv(unsigned(r.cdiv) - 1);
122 if unsigned(r.cdiv) = 0 then
123 n.dcnt := slv(unsigned(r.dcnt) + 1);
137 cano := (others=>'1');
139 cano(to_integer(unsigned(r.dcnt))) := '0';
147 end process proc_next;
156 end process proc_mux;
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 6 downto 0) slv7
std_logic_vector( 7 downto 0) slv8
slv4 :=( others => '0') CHEX
regs_type := regs_init N_REGS
regs_type := regs_init R_REGS
( 0 to 15) slv7 hex2segtbl_type
hex2segtbl_type :=( "0111111", "0000110", "1011011", "1001111", "1100110", "1101101", "1111101", "0000111", "1111111", "1101111", "1110111", "1111100", "0111001", "1011110", "1111001", "1110001") hex2segtbl
regs_type :=( slv( to_unsigned( 0, CDWIDTH) ), slv( to_unsigned( 0, DCWIDTH) )) regs_init
in DIN slv( 4*( 2** DCWIDTH)- 1 downto 0)
out ANO_N slv(( 2** DCWIDTH)- 1 downto 0)
in DP slv(( 2** DCWIDTH)- 1 downto 0)