49use ieee.std_logic_1164.
all;
50use ieee.numeric_std.
all;
140 report "assert(DAWIDTH=7 or DAWIDTH=8): unsupported DAWIDTH"
143 report "assert ALWIDTH<16: unsupported ALWIDTH"
146 report "assert(TEWIDTH=10 or TEWIDTH=12): unsupported TEWIDTH"
148 assert IBASE(2 downto 0) = "000"
149 report "assert IBASE(2:0) = 000: invalid IBASE"
155 if rising_edge(CLK) then
163 end process proc_regs;
171 variable irb_ack : slbit := '0';
172 variable irb_busy : slbit := '0';
173 variable irb_err : slbit := '0';
174 variable irb_dout : slv16 := (others=>'0');
175 variable irbena : slbit := '0';
177 variable irb_addr_ext : slbit := '0';
178 variable irb_addr_int : slbit := '0';
180 variable ism_den : slbit := '0';
181 variable ism_dwe : slbit := '0';
182 variable ism_daddr : slv(DAWIDTH-1 downto 0) := (others=>'0');
183 variable ism_reset : slbit := '0';
193 irb_dout := (others=>'0');
211 n.eoscnt := slv(unsigned(r.eoscnt) + 1);
215 n.stat_ot := r.stat_ot or SM_OT;
219 n.almh := r.almh or SM_ALM;
227 irb_ack := r.rbsel and irbena;
239 if r.tpend = '1' then
242 ism_daddr := "0000000";
248 elsif r.rbsel = '1' then
249 if irb_addr_int ='1' then
251 case RB_MREQ.addr(2 downto 0) is
259 n.stat_jlock := r.stat_jlock and
261 n.stat_jmod := r.stat_jmod and
263 n.stat_jbusy := r.stat_jbusy and
265 n.stat_ot := r.stat_ot and
271 n.almh := r.almh and not RB_MREQ.din(r.almh'range);
288 ism_daddr := RB_MREQ.addr(ism_daddr'range);
318 if r.rbsel = '1' then
319 if irb_addr_int = '1' then
320 case RB_MREQ.addr(2 downto 0) is
328 irb_dout(r.almh'range) := r.almh;
331 irb_dout(r.temp'range) := r.temp;
337 irb_dout := r.eoscnt;
340 irb_dout := (others=>'0');
363 end process proc_next;
std_logic_vector( 2 downto 0) slv3
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 7 downto 0) slv8
(s_init,s_idle,s_wait,s_twait) state_type
slv3 := "100" rbaddr_temp
integer := 15 cntl_rbf_reset
integer := 2 stat_rbf_jmod
slv3 := "000" rbaddr_cntl
slv3 := "001" rbaddr_stat
regs_type := regs_init R_REGS
integer := 1 stat_rbf_jbusy
regs_type :=( '0', s_init,( others => '0'), '0', '0', '0', '0', slv( to_unsigned( 0, ALWIDTH) ), slv( to_unsigned( 0, TEWIDTH) ), '0') regs_init
integer := 3 stat_rbf_jlock
slv3 := "010" rbaddr_almh
out SM_DADDR slv( DAWIDTH- 1 downto 0)
in SM_ALM slv( ALWIDTH- 1 downto 0)
out TEMP slv( TEWIDTH- 1 downto 0)