w11 - vhd 0.794
W11 CPU core and support modules
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rblib.vhd
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1-- $Id: rblib.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Package Name: rblib
7-- Description: Definitions for rbus interface and bus entities
8--
9-- Dependencies: -
10-- Tool versions: ise 8.2-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33
11--
12-- Revision History:
13-- Date Rev Version Comment
14-- 2016-03-12 741 4.1 add rb_sres_6
15-- 2014-09-14 593 4.0 use new rlink v4 iface and 4 bit STAT
16-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit
17-- 2011-12-23 444 3.1 CLK_CYCLE now integer
18-- 2011-08-13 405 3.0.3 add in direction for FADDR,SEL ports
19-- 2010-12-26 349 3.0.2 add rb_sel
20-- 2010-12-22 346 3.0.1 add rb_mon and rb_mon_sb;
21-- 2010-12-04 343 3.0 extracted from rrilib and rritblib;
22-- rbus V3 interface: use aval,re,we
23-- ... rrilib history removed ...
24-- 2007-09-09 81 1.0 Initial version
25------------------------------------------------------------------------------
26
27library ieee;
28use ieee.std_logic_1164.all;
29
30use work.slvtypes.all;
31
32package rblib is
33
34type rb_mreq_type is record -- rbus - master request
35 aval : slbit; -- address valid
36 re : slbit; -- read enable
37 we : slbit; -- write enable
38 init : slbit; -- init
39 addr : slv16; -- address
40 din : slv16; -- data (input to slave)
41end record rb_mreq_type;
42
44 ('0','0','0','0', -- aval, re, we, init
45 (others=>'0'), -- addr
46 (others=>'0')); -- din
47
48type rb_sres_type is record -- rbus - slave response
49 ack : slbit; -- acknowledge
50 busy : slbit; -- busy
51 err : slbit; -- error
52 dout : slv16; -- data (output from slave)
53end record rb_sres_type;
54
56 ('0','0','0', -- ack, busy, err
57 (others=>'0')); -- dout
58
59component rb_sel is -- rbus address select logic
60 generic (
61 RB_ADDR : slv16; -- rbus address base
62 SAWIDTH : natural := 0); -- device subaddress space width
63 port (
64 CLK : in slbit; -- clock
65 RB_MREQ : in rb_mreq_type; -- rbus request
66 SEL : out slbit -- select state bit
67 );
68end component;
69
70component rb_sres_or_2 is -- rbus result or, 2 input
71 port (
72 RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
73 RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
74 RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
75 );
76end component;
77component rb_sres_or_3 is -- rbus result or, 3 input
78 port (
79 RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
80 RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
81 RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
82 RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
83 );
84end component;
85component rb_sres_or_4 is -- rbus result or, 4 input
86 port (
87 RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
88 RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
89 RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
90 RB_SRES_4 : in rb_sres_type := rb_sres_init; -- rb_sres input 4
91 RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
92 );
93end component;
94component rb_sres_or_6 is -- rbus result or, 6 input
95 port (
96 RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
97 RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
98 RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
99 RB_SRES_4 : in rb_sres_type := rb_sres_init; -- rb_sres input 4
100 RB_SRES_5 : in rb_sres_type := rb_sres_init; -- rb_sres input 5
101 RB_SRES_6 : in rb_sres_type := rb_sres_init; -- rb_sres input 6
102 RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
103 );
104end component;
105
106component rbus_aif is -- rbus, abstract interface
107 port (
108 CLK : in slbit; -- clock
109 RESET : in slbit := '0'; -- reset
110 RB_MREQ : in rb_mreq_type; -- rbus: request
111 RB_SRES : out rb_sres_type; -- rbus: response
112 RB_LAM : out slv16; -- rbus: look at me
113 RB_STAT : out slv4 -- rbus: status flags
114 );
115end component;
116
117component rb_wreg_rw_3 is -- rbus: wide register r/w 3 bit select
118 generic (
119 DWIDTH : positive := 16);
120 port (
121 CLK : in slbit; -- clock
122 RESET : in slbit; -- reset
123 FADDR : in slv3; -- field address
124 SEL : in slbit; -- select
125 DATA : out slv(DWIDTH-1 downto 0); -- data
126 RB_MREQ : in rb_mreq_type; -- rbus request
127 RB_SRES : out rb_sres_type -- rbus response
128 );
129end component;
130
131component rb_wreg_w_3 is -- rbus: wide register w-o 3 bit select
132 generic (
133 DWIDTH : positive := 16);
134 port (
135 CLK : in slbit; -- clock
136 RESET : in slbit; -- reset
137 FADDR : in slv3; -- field address
138 SEL : in slbit; -- select
139 DATA : out slv(DWIDTH-1 downto 0); -- data
140 RB_MREQ : in rb_mreq_type; -- rbus request
141 RB_SRES : out rb_sres_type -- rbus response
142 );
143end component;
144
145component rb_wreg_r_3 is -- rbus: wide register r-o 3 bit select
146 generic (
147 DWIDTH : positive := 16);
148 port (
149 FADDR : in slv3; -- field address
150 SEL : in slbit; -- select
151 DATA : in slv(DWIDTH-1 downto 0); -- data
152 RB_SRES : out rb_sres_type -- rbus response
153 );
154end component;
155
156--
157-- components for use in test benches (not synthesizable)
158--
159
160component rb_sres_or_mon is -- rbus result or monitor
161 port (
162 RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
163 RB_SRES_2 : in rb_sres_type; -- rb_sres input 2
164 RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
165 RB_SRES_4 : in rb_sres_type := rb_sres_init; -- rb_sres input 4
166 RB_SRES_5 : in rb_sres_type := rb_sres_init; -- rb_sres input 5
167 RB_SRES_6 : in rb_sres_type := rb_sres_init -- rb_sres input 6
168 );
169end component;
170
171-- simbus sb_cntl field usage for rbus
172constant sbcntl_sbf_rbmon : integer := 13;
173
174component rb_mon is -- rbus monitor
175 generic (
176 DBASE : positive := 2); -- base for writing data values
177 port (
178 CLK : in slbit; -- clock
179 CLK_CYCLE : in integer := 0; -- clock cycle number
180 ENA : in slbit := '1'; -- enable monitor output
181 RB_MREQ : in rb_mreq_type; -- rbus: request
182 RB_SRES : in rb_sres_type; -- rbus: response
183 RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
184 RB_STAT : in slv4 -- rbus: status flags
185 );
186end component;
187
188component rb_mon_sb is -- simbus wrapper for rbus monitor
189 generic (
190 DBASE : positive := 2; -- base for writing data values
191 ENAPIN : integer := sbcntl_sbf_rbmon); -- SB_CNTL signal to use for enable
192 port (
193 CLK : in slbit; -- clock
194 RB_MREQ : in rb_mreq_type; -- rbus: request
195 RB_SRES : in rb_sres_type; -- rbus: response
196 RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
197 RB_STAT : in slv4 -- rbus: status flags
198 );
199end component;
200
201end package rblib;
DBASE positive := 2
Definition: rb_mon_sb.vhd:40
in CLK slbit
Definition: rb_mon_sb.vhd:43
in RB_MREQ rb_mreq_type
Definition: rb_mon_sb.vhd:44
ENAPIN integer := sbcntl_sbf_rbmon
Definition: rb_mon_sb.vhd:41
in RB_STAT slv4
Definition: rb_mon_sb.vhd:48
in RB_LAM slv16 :=( others => '0')
Definition: rb_mon_sb.vhd:46
in RB_SRES rb_sres_type
Definition: rb_mon_sb.vhd:45
DBASE positive := 2
Definition: rb_mon.vhd:46
in CLK slbit
Definition: rb_mon.vhd:48
in RB_MREQ rb_mreq_type
Definition: rb_mon.vhd:51
in CLK_CYCLE integer := 0
Definition: rb_mon.vhd:49
in ENA slbit := '1'
Definition: rb_mon.vhd:50
in RB_STAT slv4
Definition: rb_mon.vhd:55
in RB_LAM slv16 :=( others => '0')
Definition: rb_mon.vhd:53
in RB_SRES rb_sres_type
Definition: rb_mon.vhd:52
out SEL slbit
Definition: rb_sel.vhd:37
SAWIDTH natural := 0
Definition: rb_sel.vhd:32
in CLK slbit
Definition: rb_sel.vhd:34
in RB_MREQ rb_mreq_type
Definition: rb_sel.vhd:35
RB_ADDR slv16
Definition: rb_sel.vhd:31
in RB_SRES_2 rb_sres_type := rb_sres_init
out RB_SRES_OR rb_sres_type
in RB_SRES_1 rb_sres_type
in RB_SRES_2 rb_sres_type := rb_sres_init
in RB_SRES_3 rb_sres_type := rb_sres_init
out RB_SRES_OR rb_sres_type
in RB_SRES_1 rb_sres_type
in RB_SRES_2 rb_sres_type := rb_sres_init
in RB_SRES_3 rb_sres_type := rb_sres_init
out RB_SRES_OR rb_sres_type
in RB_SRES_1 rb_sres_type
in RB_SRES_4 rb_sres_type := rb_sres_init
in RB_SRES_2 rb_sres_type := rb_sres_init
in RB_SRES_3 rb_sres_type := rb_sres_init
out RB_SRES_OR rb_sres_type
in RB_SRES_1 rb_sres_type
in RB_SRES_4 rb_sres_type := rb_sres_init
in RB_SRES_5 rb_sres_type := rb_sres_init
in RB_SRES_6 rb_sres_type := rb_sres_init
in RB_SRES_2 rb_sres_type
in RB_SRES_3 rb_sres_type := rb_sres_init
in RB_SRES_1 rb_sres_type
in RB_SRES_4 rb_sres_type := rb_sres_init
in RB_SRES_5 rb_sres_type := rb_sres_init
in RB_SRES_6 rb_sres_type := rb_sres_init
Definition: rblib.vhd:32
integer := 13 sbcntl_sbf_rbmon
Definition: rblib.vhd:172
rb_mreq_type :=( '0', '0', '0', '0',( others => '0'),( others => '0')) rb_mreq_init
Definition: rblib.vhd:43
rb_sres_type
Definition: rblib.vhd:48
rb_mreq_type
Definition: rblib.vhd:34
rb_sres_type :=( '0', '0', '0',( others => '0')) rb_sres_init
Definition: rblib.vhd:55
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30