w11 - vhd 0.794
W11 CPU core and support modules
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tb_s3board_fusp.vhd
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1-- $Id: tb_s3board_fusp.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: tb_s3board_fusp - sim
7-- Description: Test bench for s3board (base+fusp)
8--
9-- Dependencies: simlib/simclk
10-- simlib/simclkcnt
11-- rlink/tbcore/tbcore_rlink
12-- tb_s3board_core
13-- s3board_fusp_aif [UUT]
14-- serport/tb/serport_master_tb
15--
16-- To test: generic, any s3board_fusp_aif target
17--
18-- Target Devices: generic
19-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.33
20-- Revision History:
21-- Date Rev Version Comment
22-- 2016-09-02 805 1.3.3 tbcore_rlink without CLK_STOP now
23-- 2016-02-13 730 1.3.2 direct instantiation of tbcore_rlink
24-- 2016-01-03 724 1.3.1 use serport/tb/serport_master_tb
25-- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx
26-- 2011-12-23 444 3.1 new system clock scheme, new tbcore_rlink iface
27-- 2011-11-19 427 3.0.1 now numeric_std clean
28-- 2010-12-30 351 3.0 use rlink/tb now
29-- 2010-11-06 336 1.0.4 rename input pin CLK -> I_CLK50
30-- 2010-05-21 292 1.0.3 rename _PM1_ -> _FUSP_
31-- 2010-05-16 291 1.0.2 rename tb_s3board_usp->tb_s3board_fusp
32-- 2010-05-02 287 1.0.1 add sbaddr_portsel def, now sbus addr 8
33-- 2010-05-01 286 1.0 Initial version (derived from tb_s3board)
34------------------------------------------------------------------------------
35
36library ieee;
37use ieee.std_logic_1164.all;
38use ieee.numeric_std.all;
39use ieee.std_logic_textio.all;
40use std.textio.all;
41
42use work.slvtypes.all;
43use work.rlinklib.all;
44use work.s3boardlib.all;
45use work.simlib.all;
46use work.simbus.all;
47
50
51architecture sim of tb_s3board_fusp is
52
53 signal CLK : slbit := '0';
54
55 signal CLK_CYCLE : integer := 0;
56
57 signal RESET : slbit := '0';
58 signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
59 signal RXDATA : slv8 := (others=>'0');
60 signal RXVAL : slbit := '0';
61 signal RXERR : slbit := '0';
62 signal RXACT : slbit := '0';
63 signal TXDATA : slv8 := (others=>'0');
64 signal TXENA : slbit := '0';
65 signal TXBUSY : slbit := '0';
66
67 signal RX_HOLD : slbit := '0';
68
69 signal I_RXD : slbit := '1';
70 signal O_TXD : slbit := '1';
71 signal I_SWI : slv8 := (others=>'0');
72 signal I_BTN : slv4 := (others=>'0');
73 signal O_LED : slv8 := (others=>'0');
74 signal O_ANO_N : slv4 := (others=>'0');
75 signal O_SEG_N : slv8 := (others=>'0');
76
77 signal O_MEM_CE_N : slv2 := (others=>'1');
78 signal O_MEM_BE_N : slv4 := (others=>'1');
79 signal O_MEM_WE_N : slbit := '1';
80 signal O_MEM_OE_N : slbit := '1';
81 signal O_MEM_ADDR : slv18 := (others=>'Z');
82 signal IO_MEM_DATA : slv32 := (others=>'0');
83
84 signal O_FUSP_RTS_N : slbit := '0';
85 signal I_FUSP_CTS_N : slbit := '0';
86 signal I_FUSP_RXD : slbit := '1';
87 signal O_FUSP_TXD : slbit := '1';
88
89 signal UART_RESET : slbit := '0';
90 signal UART_RXD : slbit := '1';
91 signal UART_TXD : slbit := '1';
92 signal CTS_N : slbit := '0';
93 signal RTS_N : slbit := '0';
94
95 signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport
96 signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
97
98 constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
99
100 constant clock_period : Delay_length := 20 ns;
101 constant clock_offset : Delay_length := 200 ns;
102
103begin
104
105 CLKGEN : simclk
106 generic map (
109 port map (
110 CLK => CLK
111 );
112
113 CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
114
115 TBCORE : entity work.tbcore_rlink
116 port map (
117 CLK => CLK,
118 RX_DATA => TXDATA,
119 RX_VAL => TXENA,
120 RX_HOLD => RX_HOLD,
121 TX_DATA => RXDATA,
122 TX_ENA => RXVAL
123 );
124
125 RX_HOLD <= TXBUSY or RTS_N; -- back pressure for data flow to tb
126
127 S3CORE : entity work.tb_s3board_core
128 port map (
129 I_SWI => I_SWI,
130 I_BTN => I_BTN,
137 );
138
139 UUT : s3board_fusp_aif
140 port map (
141 I_CLK50 => CLK,
142 I_RXD => I_RXD,
143 O_TXD => O_TXD,
144 I_SWI => I_SWI,
145 I_BTN => I_BTN,
146 O_LED => O_LED,
147 O_ANO_N => O_ANO_N,
148 O_SEG_N => O_SEG_N,
149 O_MEM_CE_N => O_MEM_CE_N,
150 O_MEM_BE_N => O_MEM_BE_N,
151 O_MEM_WE_N => O_MEM_WE_N,
152 O_MEM_OE_N => O_MEM_OE_N,
153 O_MEM_ADDR => O_MEM_ADDR,
154 IO_MEM_DATA => IO_MEM_DATA,
155 O_FUSP_RTS_N => O_FUSP_RTS_N,
156 I_FUSP_CTS_N => I_FUSP_CTS_N,
157 I_FUSP_RXD => I_FUSP_RXD,
158 O_FUSP_TXD => O_FUSP_TXD
159 );
160
161 SERMSTR : entity work.serport_master_tb
162 generic map (
163 CDWIDTH => CLKDIV'length)
164 port map (
165 CLK => CLK,
166 RESET => UART_RESET,
167 CLKDIV => CLKDIV,
169 ENAESC => '0',
170 RXDATA => RXDATA,
171 RXVAL => RXVAL,
172 RXERR => RXERR,
173 RXOK => '1',
174 TXDATA => TXDATA,
175 TXENA => TXENA,
176 TXBUSY => TXBUSY,
177 RXSD => UART_RXD,
178 TXSD => UART_TXD,
179 RXRTS_N => RTS_N,
180 TXCTS_N => CTS_N
181 );
182
183 proc_port_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N,
185 begin
186
187 if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl
188 I_RXD <= UART_TXD; -- write port 0 inputs
189 UART_RXD <= O_TXD; -- get port 0 outputs
190 RTS_N <= '0';
191 I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
192 I_FUSP_CTS_N <= '0';
193 else -- otherwise use pmod1 rs232
194 I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
196 UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
198 I_RXD <= '1'; -- port 0 inputs to idle state
199 end if;
200
201 end process proc_port_mux;
202
203 proc_moni: process
204 variable oline : line;
205 begin
206
207 loop
208 wait until rising_edge(CLK);
209
210 if RXERR = '1' then
211 writetimestamp(oline, CLK_CYCLE, " : seen RXERR=1");
212 writeline(output, oline);
213 end if;
214
215 end loop;
216
217 end process proc_moni;
218
219 proc_simbus: process (SB_VAL)
220 begin
221 if SB_VAL'event and to_x01(SB_VAL)='1' then
222 if SB_ADDR = sbaddr_portsel then
223 R_PORTSEL_SER <= to_x01(SB_DATA(0));
224 R_PORTSEL_XON <= to_x01(SB_DATA(1));
225 end if;
226 end if;
227 end process proc_simbus;
228
229end sim;
CDWIDTH positive := 13
in ENAESC slbit := '0'
in ENAXON slbit := '0'
in CLKDIV slv( CDWIDTH- 1 downto 0)
in RXOK slbit := '1'
in TXCTS_N slbit := '0'
out CLK slbit
Definition: simclk.vhd:33
OFFSET Delay_length := 200 ns
Definition: simclk.vhd:31
PERIOD Delay_length := 20 ns
Definition: simclk.vhd:30
out CLK_CYCLE integer
Definition: simclkcnt.vhd:29
in CLK slbit
Definition: simclkcnt.vhd:27
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 17 downto 0) slv18
Definition: slvtypes.vhd:51
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
std_logic_vector slv
Definition: slvtypes.vhd:31
inout IO_MEM_DATA slv32
in O_MEM_WE_N slbit
in O_MEM_ADDR slv18
in O_MEM_OE_N slbit
slv8 :=( others => '0') O_SEG_N
slv4 :=( others => '1') O_MEM_BE_N
slbit := '1' I_FUSP_RXD
slv4 :=( others => '0') I_BTN
slv8 :=( others => '0') RXDATA
Delay_length := 200 ns clock_offset
slbit := '1' O_FUSP_TXD
slv8 :=( others => '0') O_LED
slbit := '0' R_PORTSEL_SER
slv18 :=( others => 'Z') O_MEM_ADDR
slbit := '0' UART_RESET
slv32 :=( others => '0') IO_MEM_DATA
slv8 := slv( to_unsigned( 8, 8) ) sbaddr_portsel
integer := 0 CLK_CYCLE
slv2 :=( others => '1') O_MEM_CE_N
slbit := '1' O_MEM_OE_N
slv8 :=( others => '0') I_SWI
slv4 :=( others => '0') O_ANO_N
slbit := '0' R_PORTSEL_XON
slbit := '1' O_MEM_WE_N
slbit := '0' O_FUSP_RTS_N
slv8 :=( others => '0') TXDATA
Delay_length := 20 ns clock_period
slbit := '0' I_FUSP_CTS_N