37use ieee.std_logic_1164.
all;
38use ieee.numeric_std.
all;
39use ieee.std_logic_textio.
all;
139 UUT : s3board_fusp_aif
201 end process proc_port_mux;
204 variable oline : line;
208 wait until rising_edge(CLK);
211 writetimestamp(oline, CLK_CYCLE, " : seen RXERR=1");
212 writeline(output, oline);
217 end process proc_moni;
219 proc_simbus:
process (SB_VAL)
221 if SB_VAL'event and to_x01(SB_VAL)='1' then
227 end process proc_simbus;
in CLKDIV slv( CDWIDTH- 1 downto 0)
OFFSET Delay_length := 200 ns
PERIOD Delay_length := 20 ns
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 17 downto 0) slv18
std_logic_vector( 31 downto 0) slv32
std_logic_vector( 7 downto 0) slv8
std_logic_vector( 1 downto 0) slv2
slv8 :=( others => '0') O_SEG_N
slv4 :=( others => '1') O_MEM_BE_N
slv4 :=( others => '0') I_BTN
slv8 :=( others => '0') RXDATA
Delay_length := 200 ns clock_offset
slv8 :=( others => '0') O_LED
slbit := '0' R_PORTSEL_SER
slv18 :=( others => 'Z') O_MEM_ADDR
slv32 :=( others => '0') IO_MEM_DATA
slv8 := slv( to_unsigned( 8, 8) ) sbaddr_portsel
slv2 :=( others => '1') O_MEM_CE_N
slv8 :=( others => '0') I_SWI
slv4 :=( others => '0') O_ANO_N
slbit := '0' R_PORTSEL_XON
slbit := '0' O_FUSP_RTS_N
slv8 :=( others => '0') TXDATA
Delay_length := 20 ns clock_period
slbit := '0' I_FUSP_CTS_N