46use ieee.std_logic_1164.
all;
47use ieee.numeric_std.
all;
48use ieee.std_logic_textio.
all;
61procedure readoct( -- read
slv in octal
base (arb.
length)
62 L:
inout line; -- line
63 value:
out std_logic_vector; --
value to be read
67 L:
inout line; -- line
68 value:
out std_logic_vector; --
value to be read
72 L:
inout line; -- line
73 value:
out std_logic_vector; --
value to be read
74 good:
out boolean; -- success flag
75 base:
in integer:=
2);
116 imin :
in integer := integer'low;
117 imax :
in integer := integer'high);
121 value:
out std_logic);
124 value:
out std_logic_vector);
128 value:
out std_logic_vector);
132 value:
out std_logic_vector);
136 value:
out std_logic_vector;
137 base:
in integer:=
2);
147 val:
out std_logic_vector;
149 base:
in integer:=
2);
154 val:
out std_logic_vector;
155 base:
in integer:=
2);
173 val1:
out std_logic_vector;
174 val2:
out std_logic_vector;
176 base:
in integer:=
2);
181 val1:
out std_logic_vector;
182 val2:
out std_logic_vector;
183 base:
in integer:=
2);
186 L:
inout line; -- line
187 value:
in std_logic_vector; --
value to be written
188 justified:
in side:=right; -- justification (left/right)
192 L:
inout line; -- line
193 value:
in std_logic_vector; --
value to be written
194 justified:
in side:=right; -- justification (left/right)
198 L:
inout line; -- line
199 value:
in std_logic_vector; --
value to be written
200 justified:
in side:=right; -- justification (left/right)
201 field:
in width:=0; -- field width
202 base:
in integer:=
2);
205 L:
inout line; -- line
207 field :
in width:=0);
210 L:
inout line; -- line
214 L:
inout line; -- line
215 clkcyc:
in integer; -- cycle number
219 L:
inout line; -- line
220 str :
in string; --
string
221 dat :
in integer; -- int
value
227 str :
in string; --
string
230 str :
in string; --
string
233 str :
in string; --
string
237 period
: Delay_length;
239 setup : Delay_length;
243 signal clk :
in slbit; -- clock
244 constant clk_dsc :
in clock_dsc; -- clock descriptor
245 constant cnt :
in positive :=
1);
248 signal clk :
in slbit; -- clock
249 constant clk_dsc :
in clock_dsc; -- clock descriptor
250 constant cnt :
in positive :=
1);
253 signal clk :
in slbit; -- clock
257 signal clk :
in slbit; -- clock
258 constant clk_dsc :
in clock_dsc; -- clock descriptor
259 signal sig :
in slbit; --
signal
260 constant val :
in slbit; --
value
261 variable cnt :
out natural);
263type simfifo_type is array (natural range <>, natural range<>) of std_logic;
266 cnt :
inout natural; -- fifo element count
268 din :
in std_logic_vector; -- element
to add
269 val :
in slbit := '1');
272 cnt :
inout natural; -- fifo element count
274 dout:
out std_logic_vector);
277 L:
inout line; -- line
278 cnt :
inout natural; -- fifo element count
280 dat :
in std_logic_vector);
283 cnt :
inout natural; -- fifo element count
291 PERIOD : Delay_length :=
20 ns;
292 OFFSET : Delay_length :=
200 ns);
318 DELAY : Delay_length;
333 L:
inout line)
is -- line
334 variable ch :
character;
336 while L'
length>
0 loop
338 exit when (ch/=' '
and ch/=HT
);
342end procedure readwhite;
346procedure readoct
( -- read slv in octal base (arb. length)
347 L:
inout line;
-- line
348 value:
out std_logic_vector;
-- value to be read
349 good:
out boolean) is -- success flag
351 variable nibble :
std_logic_vector(2 downto 0);
352 variable sum :
std_logic_vector(31 downto 0);
353 variable ndig :
integer;
-- number of digits
354 variable ok :
boolean;
355 variable ichar :
character;
359 assert not value'
ascending(1)
360 report "readoct called with ascending range"
362 assert value'
length<=
32
363 report "readoct called with value'length > 32"
369 sum :=
(others=>'U'
);
371 while L'
length>
0 loop
374 when '
0' => nibble :=
"000";
375 when '
1' => nibble :=
"001";
376 when '
2' => nibble :=
"010";
377 when '
3' => nibble :=
"011";
378 when '
4' => nibble :=
"100";
379 when '
5' => nibble :=
"101";
380 when '
6' => nibble :=
"110";
381 when '
7' => nibble :=
"111";
382 when 'u'|'U' => nibble :=
"UUU";
383 when 'x'|'X' => nibble :=
"XXX";
384 when 'z'|'Z' => nibble :=
"ZZZ";
385 when '-' => nibble :=
"---";
386 when others => ok := false;
392 sum
(sum'
left downto 3) := sum
(sum'
left-
3 downto 0);
393 sum
(2 downto 0) := nibble;
397 value := sum
(value'
range);
400end procedure readoct;
404procedure readhex
( -- read slv in hex base (arb. length)
405 L:
inout line;
-- line
406 value:
out std_logic_vector;
-- value to be read
407 good:
out boolean) is -- success flag
409 variable nibble :
std_logic_vector(3 downto 0);
410 variable sum :
std_logic_vector(31 downto 0);
411 variable ndig :
integer;
-- number of digits
412 variable ok :
boolean;
413 variable ichar :
character;
417 assert not value'
ascending(1)
418 report "readhex called with ascending range"
420 assert value'
length<=
32
421 report "readhex called with value'length > 32"
427 sum :=
(others=>'U'
);
429 while L'
length>
0 loop
432 when '
0' => nibble :=
"0000";
433 when '
1' => nibble :=
"0001";
434 when '
2' => nibble :=
"0010";
435 when '
3' => nibble :=
"0011";
436 when '
4' => nibble :=
"0100";
437 when '
5' => nibble :=
"0101";
438 when '
6' => nibble :=
"0110";
439 when '
7' => nibble :=
"0111";
440 when '
8' => nibble :=
"1000";
441 when '
9' => nibble :=
"1001";
442 when 'a'|'A' => nibble :=
"1010";
443 when 'b'|'B' => nibble :=
"1011";
444 when 'c'|'C' => nibble :=
"1100";
445 when 'd'|'D' => nibble :=
"1101";
446 when 'e'|'E' => nibble :=
"1110";
447 when 'f'|'F' => nibble :=
"1111";
448 when 'u'|'U' => nibble :=
"UUUU";
449 when 'x'|'X' => nibble :=
"XXXX";
450 when 'z'|'Z' => nibble :=
"ZZZZ";
451 when '-' => nibble :=
"----";
452 when others => ok := false;
458 sum
(sum'
left downto 4) := sum
(sum'
left-
4 downto 0);
459 sum
(3 downto 0) := nibble;
463 value := sum
(value'
range);
466end procedure readhex;
470procedure readgen
( -- read slv generic base
471 L:
inout line;
-- line
472 value:
out std_logic_vector;
-- value to be read
473 good:
out boolean;
-- success flag
474 base:
in integer :=
2) is -- default base
476 variable nibble :
std_logic_vector(3 downto 0);
477 variable sum :
std_logic_vector(31 downto 0);
478 variable lbase :
integer;
-- local base
479 variable cbase :
integer;
-- current base
480 variable ok :
boolean;
481 variable ivalue :
integer;
482 variable ichar :
character;
486 assert not value'
ascending(1)
487 report "readgen called with ascending range"
489 assert value'
length<=
32
490 report "readgen called with value'length > 32"
492 assert base=
2 or base=
8 or base=
10 or base=
16
493 report "readgen base not 2,8,10, or 16"
502 if L'
length >=
2 then
503 if L
(L'
left+
1) = '"'
then
505 when 'b'|'B' => lbase :=
2;
506 when 'o'|'O' => lbase :=
8;
507 when 'd'|'D' => lbase :=
10;
508 when 'x'|'X' => lbase :=
16;
509 when others => ok := false;
521 when 2 => read
(L,
value, ok
);
522 when 8 => readoct
(L,
value, ok
);
523 when 16 => readhex
(L,
value, ok
);
528 value :=
slv(to_unsigned
(ivalue,
value'
length));
530 value :=
slv(to_signed
(ivalue,
value'
length));
536 if ok
and lbase/=
0 then
537 if L'
length>
0 and L
(L'
left)='"'
then
546end procedure readgen;
550procedure readcomment
(
552 good:
out boolean) is
553 variable ichar :
character;
561 if L
(L'
left) = '#'
then
563 elsif L
(L'
left) = 'C'
then
565 writeline
(output, L
);
569end procedure readcomment;
573procedure readdotcomm
(
576 good:
out boolean) is
579 for i
in name'
range loop
584 if L'
length>
0 and L
(L'
left)='.'
then
585 readword
(L, name, good
);
588end procedure readdotcomm;
595 good:
out boolean) is
597 variable ichar :
character;
598 variable ind :
integer;
602 assert name'
ascending(1)
603 report "readword called with descending range for name"
608 for i
in name'
range loop
613 while L'
length>
0 and ind<=name'
right loop
615 exit when ichar=' '
or ichar=','
or ichar='|';
621 good := ind /= name'
left;
-- ok if one non-blank found
623end procedure readword;
627procedure readoptchar
(
630 good:
out boolean) is
632 variable ichar :
character;
638 if L
(L'
left) = char
then
644end procedure readoptchar;
651 variable ch :
character;
655 while L'
length>
0 loop -- anything left ?
656 read
(L,ch
);
-- read and discard it
659end procedure readempty;
665 good:
out boolean) is
669 readwhite
(L
);
-- discard white space
670 good := true;
-- good if now empty
672 if L'
length >
0 then -- anything left ?
673 good := false;
-- assume bad
674 if L'
length >=
2 and -- check for "--"
675 L
(L'
left)='-'
and L
(L'
left+
1)='-'
then
676 good := true;
-- in that case comment -> good
680end procedure testempty;
684procedure testempty_ea
(
687 variable ok :
boolean := false;
692 assert ok
report "extra chars in """ & L.
all & """"
severity failure;
694end procedure testempty_ea;
700 value:
out integer) is
702 variable ok :
boolean := false;
707 assert ok
report "read(integer) conversion error in """ &
708 L.
all & """"
severity failure;
710end procedure read_ea;
718 variable ok :
boolean := false;
723 assert ok
report "read(time) conversion error in """ &
724 L.
all & """"
severity failure;
726end procedure read_ea;
733 imin :
in integer :=
integer'
low;
734 imax :
in integer :=
integer'
high) is
736 variable dat :
integer :=
0;
741 assert dat>=imin
and dat<=imax
742 report "readint_ea range check: " &
743 integer'
image(dat
) &
" not in " &
744 integer'
image(imin
) &
":" &
integer'
image(imax
)
747end procedure readint_ea;
753 value:
out std_logic) is
755 variable ok :
boolean := false;
760 assert ok
report "read(std_logic) conversion error in """ &
761 L.
all & """"
severity failure;
763end procedure read_ea;
769 value:
out std_logic_vector) is
771 variable ok :
boolean := false;
776 assert ok
report "read(std_logic_vector) conversion error in """ &
777 L.
all & """"
severity failure;
779end procedure read_ea;
785 value:
out std_logic_vector) is
787 variable ok :
boolean := false;
791 readoct
(L,
value, ok
);
792 assert ok
report "readoct() conversion error in """ &
793 L.
all & """"
severity failure;
795end procedure readoct_ea;
801 value:
out std_logic_vector) is
803 variable ok :
boolean := false;
807 readhex
(L,
value, ok
);
808 assert ok
report "readhex() conversion error in """ &
809 L.
all & """"
severity failure;
811end procedure readhex_ea;
817 value:
out std_logic_vector;
818 base:
in integer :=
2) is
820 variable ok :
boolean := false;
824 readgen
(L,
value, ok,
base);
825 assert ok
report "readgen() conversion error in """ &
826 L.
all & """"
severity failure;
828end procedure readgen_ea;
832procedure readword_ea
(
836 variable ok :
boolean := false;
840 readword
(L, name, ok
);
841 assert ok
report "readword() read error in """ &
842 L.
all & """"
severity failure;
844end procedure readword_ea;
852 val:
out std_logic_vector;
854 base:
in integer:=
2) is
856 variable itag :
string(tag'
range);
857 variable ichar :
character;
858 variable imatch :
boolean;
864 for i
in val'
range loop
870 if L'
length > tag'
length then
871 imatch := L
(L'
left to L'
left+tag'
length-
1) = tag
and
872 L
(L'
left+tag'
length) = '=';
876 readgen
(L,
val, good,
base);
881end procedure readtagval;
885procedure readtagval_ea
(
889 val:
out std_logic_vector;
890 base:
in integer:=
2) is
892 variable ok :
boolean := false;
895 readtagval
(L, tag, match,
val, ok,
base);
896 assert ok
report "readtagval(std_logic_vector) conversion error in """ &
897 L.
all & """"
severity failure;
898end procedure readtagval_ea;
907 good:
out boolean) is
909 variable itag :
string(tag'
range);
910 variable ichar :
character;
911 variable imatch :
boolean;
921 if L'
length > tag'
length then
922 imatch := L
(L'
left to L'
left+tag'
length-
1) = tag
and
923 L
(L'
left+tag'
length) = '=';
932end procedure readtagval;
936procedure readtagval_ea
(
940 val:
out std_logic) is
942 variable ok :
boolean := false;
945 readtagval
(L, tag, match,
val, ok
);
946 assert ok
report "readtagval(std_logic) conversion error in """ &
947 L.
all & """"
severity failure;
948end procedure readtagval_ea;
952procedure readtagval2
(
956 val1:
out std_logic_vector;
957 val2:
out std_logic_vector;
959 base:
in integer:=
2) is
961 variable itag :
string(tag'
range);
962 variable imatch :
boolean;
963 variable igood :
boolean;
964 variable ichar :
character;
965 variable ok :
boolean;
971 for i
in val1'
range loop -- zero val1
974 for i
in val2'
range loop -- zero val2
980 if L'
length > tag'
length then -- check for tag
981 imatch := L
(L'
left to L'
left+tag'
length-
1) = tag
and
982 L
(L'
left+tag'
length) = '=';
984 if imatch
then -- if found
985 read
(L, itag
);
-- remove tag
986 read
(L, ichar
);
-- remove =
989 readoptchar
(L, '-', ok
);
-- check for tag=-
991 for i
in val2'
range loop -- set mask to all 1 (ignore)
995 else -- here if tag=bit[,bit]
996 readgen
(L, val1, igood,
base);
-- read val1
998 readoptchar
(L, ',', ok
);
-- check(and remove) ,
1000 readgen
(L, val2, igood,
base);
-- and read val2
1010end procedure readtagval2;
1014procedure readtagval2_ea
(
1018 val1:
out std_logic_vector;
1019 val2:
out std_logic_vector;
1020 base:
in integer:=
2) is
1022 variable ok :
boolean := false;
1025 readtagval2
(L, tag, match, val1, val2, ok,
base);
1026 assert ok
report "readtagval2() conversion error in """ &
1027 L.
all & """"
severity failure;
1028end procedure readtagval2_ea;
1032procedure writeoct
( -- write slv in octal base (arb. length)
1033 L:
inout line;
-- line
1034 value:
in std_logic_vector;
-- value to be written
1035 justified:
in side:=
right;
-- justification (left/right)
1036 field:
in width:=
0) is -- field width
1038 variable nbit :
integer;
-- number of bits
1039 variable ndig :
integer;
-- number of digits
1040 variable iwidth :
integer;
1041 variable ioffset :
integer;
1042 variable nibble :
std_logic_vector(2 downto 0);
1043 variable ochar :
character;
1047 assert not value'
ascending(1)
1048 report "writeoct called with ascending range"
1051 nbit :=
value'
length(1);
1053 iwidth := nbit
mod 3;
1057 ioffset :=
value'
left(1) - iwidth+
1;
1058 if justified=
right and field>ndig
then
1059 for i
in ndig+
1 to field
loop
1063 for i
in 0 to ndig-
1 loop
1065 nibble
(iwidth-
1 downto 0) :=
value(ioffset+iwidth-
1 downto ioffset
);
1067 for j
in nibble'
range loop
1069 when 'U' => ochar := 'U';
1070 when 'X' => ochar := 'X';
1071 when 'Z' => ochar := 'Z';
1072 when '-' => ochar := '-';
1073 when others =>
null;
1077 write
(L,to_integer
(unsigned(nibble
)));
1082 ioffset := ioffset -
3;
1084 if justified=
left and field>ndig
then
1085 for i
in ndig+
1 to field
loop
1089end procedure writeoct;
1093procedure writehex
( -- write slv in hex base (arb. length)
1094 L:
inout line;
-- line
1095 value:
in std_logic_vector;
-- value to be written
1096 justified:
in side:=
right;
-- justification (left/right)
1097 field:
in width:=
0) is -- field width
1099 variable nbit :
integer;
-- number of bits
1100 variable ndig :
integer;
-- number of digits
1101 variable iwidth :
integer;
1102 variable ioffset :
integer;
1103 variable nibble :
std_logic_vector(3 downto 0);
1104 variable ochar :
character;
1105 variable hextab :
string(1 to 16) :=
"0123456789abcdef";
1109 assert not value'
ascending(1)
1110 report "writehex called with ascending range"
1113 nbit :=
value'
length(1);
1115 iwidth := nbit
mod 4;
1119 ioffset :=
value'
left(1) - iwidth+
1;
1120 if justified=
right and field>ndig
then
1121 for i
in ndig+
1 to field
loop
1125 for i
in 0 to ndig-
1 loop
1127 nibble
(iwidth-
1 downto 0) :=
value(ioffset+iwidth-
1 downto ioffset
);
1129 for j
in nibble'
range loop
1131 when 'U' => ochar := 'U';
1132 when 'X' => ochar := 'X';
1133 when 'Z' => ochar := 'Z';
1134 when '-' => ochar := '-';
1135 when others =>
null;
1139 write
(L,hextab
(to_integer
(unsigned(nibble
))+
1));
1144 ioffset := ioffset -
4;
1146 if justified=
left and field>ndig
then
1147 for i
in ndig+
1 to field
loop
1151end procedure writehex;
1155procedure writegen
( -- write slv in generic base (arb. lth)
1156 L:
inout line;
-- line
1157 value:
in std_logic_vector;
-- value to be written
1158 justified:
in side:=
right;
-- justification (left/right)
1159 field:
in width:=
0;
-- field width
1160 base:
in integer:=
2) is -- default base
1165 when 2 => write
(L,
value, justified, field
);
1166 when 8 => writeoct
(L,
value, justified, field
);
1167 when 16 => writehex
(L,
value, justified, field
);
1168 when others =>
report "writegen base not 2,8, or 16"
1172end procedure writegen;
1175procedure writetimens
( -- write time as fractional ns
1176 L:
inout line;
-- line
1177 t :
in time;
-- time
1178 field :
in width:=
0) is -- number of ns digits
1180 variable t_nsec :
integer :=
0;
1181 variable t_psec :
integer :=
0;
1182 variable t_dnsec :
integer :=
0;
1187 t_psec :=
(t - t_nsec *
1 ns
) /
1 ps;
1188 t_dnsec := t_psec/
100;
1190 write
(L, t_nsec,
right, field
);
1192 write
(L, t_dnsec,
right,
1);
1193 write
(L,
string'
(" ns"));
1195end procedure writetimens;
1199procedure writetimestamp
(
1205 writetimens
(L, now,
8);
1210end procedure writetimestamp;
1214procedure writetimestamp
(
1223 write
(L, clkcyc,
right,
7);
1228end procedure writetimestamp;
1232procedure writeoptint
( -- write int if > 0
1233 L:
inout line;
-- line
1234 str :
in string;
-- string
1235 dat :
in integer;
-- int value
1236 field:
in width:=
0) is -- field width
1242 write
(L, dat,
right, field
);
1245end procedure writeoptint;
1249procedure writetrace
( -- debug trace - plain
1250 str:
in string) is -- string
1252 variable oline : line;
1256 writetimestamp
(oline,
" ++ ");
1258 writeline
(output, oline
);
1260end procedure writetrace;
1264procedure writetrace
( -- debug trace - int
1265 str:
in string;
-- string
1266 dat :
in integer) is -- value
1268 variable oline : line;
1272 writetimestamp
(oline,
" ++ ");
1275 writeline
(output, oline
);
1277end procedure writetrace;
1281procedure writetrace
( -- debug trace - slbit
1282 str:
in string;
-- string
1283 dat :
in slbit) is -- value
1285 variable oline : line;
1289 writetimestamp
(oline,
" ++ ");
1292 writeline
(output, oline
);
1294end procedure writetrace;
1298procedure writetrace
( -- debug trace - slv
1299 str:
in string;
-- string
1300 dat :
in slv) is -- value
1302 variable oline : line;
1306 writetimestamp
(oline,
" ++ ");
1309 writeline
(output, oline
);
1311end procedure writetrace;
1315procedure wait_nextstim
( -- wait for next stim time
1316 signal clk :
in slbit;
-- clock
1317 constant clk_dsc :
in clock_dsc;
-- clock descriptor
1318 constant cnt :
in positive :=
1) is -- number of cycles to wait
1322 for i
in 1 to cnt
loop
1323 wait until rising_edge
(clk
);
1324 wait for clk_dsc.hold;
1327end procedure wait_nextstim;
1331procedure wait_nextmoni
( -- wait for next moni time
1332 signal clk :
in slbit;
-- clock
1333 constant clk_dsc :
in clock_dsc;
-- clock descriptor
1334 constant cnt :
in positive :=
1) is -- number of cycles to wait
1338 for i
in 1 to cnt
loop
1339 wait until rising_edge
(clk
);
1340 wait for clk_dsc.period - clk_dsc.setup;
1343end procedure wait_nextmoni;
1347procedure wait_stim2moni
( -- wait from stim to moni time
1348 signal clk :
in slbit;
-- clock
1349 constant clk_dsc :
in clock_dsc) is -- clock descriptor
1353 wait for clk_dsc.period - clk_dsc.hold - clk_dsc.setup;
1355end procedure wait_stim2moni;
1359procedure wait_untilsignal
( -- wait until signal
1360 signal clk :
in slbit;
-- clock
1361 constant clk_dsc :
in clock_dsc;
-- clock descriptor
1362 signal sig :
in slbit;
-- signal
1363 constant val :
in slbit;
-- value
1364 variable cnt :
out natural) is -- cycle count
1366 variable cnt_l :
natural :=
0;
1370 while val /= sig
loop
1371 wait_nextmoni
(clk, clk_dsc
);
1376end procedure wait_untilsignal;
1380procedure simfifo_put
( -- add item to simfifo
1381 cnt :
inout natural;
-- fifo element count
1383 din :
in std_logic_vector;
-- element to add
1384 val :
in slbit := '
1'
) is -- valid flag
1386 variable din_imax :
integer := din'
length-
1;
1393 assert cnt < arr'
high(1)
1394 report "simfifo_put: fifo full"
1396 assert arr'
length(2) = din'
length and
1397 arr'
ascending(2) = din'
ascending
1398 report "simfifo_put: arr,din range mismatch"
1401 for i
in 0 to din_imax
loop
1402 arr
(cnt, arr'
low(2)+i
) := din
(din'
low+i
);
1406end procedure simfifo_put;
1410procedure simfifo_get
( -- get item from simfifo
1411 cnt :
inout natural;
-- fifo element count
1413 dout :
out std_logic_vector) is -- element retrieved
1415 variable dout_imax :
integer := dout'
length-
1;
1419 report "simfifo_put: fifo empty"
1421 assert arr'
length(2) = dout'
length and
1422 arr'
ascending(2) = dout'
ascending
1423 report "simfifo_put: arr,din range mismatch"
1426 for i
in 0 to dout_imax
loop
1427 dout
(dout'
low+i
) := arr
(0, arr'
low(2)+i
);
1431 for i
in 1 to cnt
loop
1432 for j
in 0 to dout_imax
loop
1433 arr
(i-
1, arr'
low(2)+j
) := arr
(i, arr'
low(2)+j
);
1438end procedure simfifo_get;
1442procedure simfifo_writetest
( -- test value against simfifo and write
1443 L:
inout line;
-- line
1444 cnt :
inout natural;
-- fifo element count
1446 dat :
in std_logic_vector) is -- data to test
1448 variable refdata :
slv(dat'
range);
1453 write
(L,
string'
(" FAIL: UNEXPECTED"));
1455 simfifo_get
(cnt, arr, refdata
);
1456 write
(L,
string'
(" CHECK: "));
1457 if dat = refdata
then
1458 write
(L,
string'
("OK"));
1460 write
(L,
string'
("FAIL, EXP= "));
1465end procedure simfifo_writetest;
1469procedure simfifo_dump
( -- dump simfifo
1470 cnt :
inout natural;
-- fifo element count
1474 variable oline : line;
1475 variable data :
slv(arr'
range(2));
1479 writetimestamp
(oline,
" ++ ");
1483 write
(oline,
string'
(" cnt= "));
1485 write
(oline,
string'
(" of "));
1486 write
(oline, arr'
high(1));
1487 write
(oline,
string'
("; drange="));
1488 write
(oline, arr'
left(2));
1489 if arr'
ascending(2) then
1490 write
(oline,
string'
(" to "));
1492 write
(oline,
string'
(" downto "));
1494 write
(oline, arr'
right(2));
1495 writeline
(output, oline
);
1498 for i
in 0 to cnt-
1 loop
1499 for j
in data'
range loop
1500 data
(j
) := arr
(i,j
);
1502 write
(oline,
string'
(" - "));
1503 write
(oline, i,
right,
2);
1504 write
(oline,
string'
(" "));
1506 writeline
(output, oline
);
1510end procedure simfifo_dump;
1512end package body simlib;
inout B slv( DWIDTH- 1 downto 0)
inout A slv( DWIDTH- 1 downto 0)
OFFSET Delay_length := 200 ns
PERIOD Delay_length := 20 ns
in CLK_PERIOD Delay_length
wait_untilsignalclk,clk_dsc,sig,val,cnt,
readint_eaL,value,imin,imax,
readtagval2_eaL,tag,match,val1,val2,base,
writeoptintL,str,dat,field,
wait_nextmoniclk,clk_dsc,cnt,
array(natural range <> ,natural range <> ) of std_logic simfifo_type
readtagval2L,tag,match,val1,val2,good,base,
readgenL,value,good,base,
string( 1 to 1) :=( others => null_char) null_string
writegenL,value,justified,field,base,
writehexL,value,justified,field,
wait_nextstimclk,clk_dsc,cnt,
wait_stim2moniclk,clk_dsc,
readtagvalL,tag,match,val,good,base,
writeoctL,value,justified,field,
simfifo_writetestL,cnt,arr,dat,
readtagval_eaL,tag,match,val,base,
simfifo_putcnt,arr,din,val,
character := character'val( 0) null_char