w11 - vhd 0.794
W11 CPU core and support modules
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bp_rs232_2line_iob.vhd
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1-- $Id: bp_rs232_2line_iob.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: bp_rs232_2line_iob - syn
7-- Description: iob's for 2 line rs232 (RXD,TXD only)
8--
9-- Dependencies: xlib/iob_reg_i
10-- xlib/iob_reg_o
11--
12-- Test bench: -
13--
14-- Target Devices: generic
15-- Tool versions: xst 11.4-14.7; viv 2014.4; ghdl 0.26-0.31
16--
17-- Revision History:
18-- Date Rev Version Comment
19-- 2011-07-01 386 1.1 Moved and renamed to bpgen
20-- 2010-04-17 278 1.0 Initial version (as s3_rs232_iob_int)
21------------------------------------------------------------------------------
22--
23
24library ieee;
25use ieee.std_logic_1164.all;
26
27use work.slvtypes.all;
28use work.xlib.all;
29
30-- ----------------------------------------------------------------------------
31
32entity bp_rs232_2line_iob is -- iob's for 2 line rs232 (RXD,TXD)
33 port (
34 CLK : in slbit; -- clock
35 RXD : out slbit; -- receive data (board view)
36 TXD : in slbit; -- transmit data (board view)
37 I_RXD : in slbit; -- pad-i: receive data (board view)
38 O_TXD : out slbit -- pad-o: transmit data (board view)
39 );
41
42architecture syn of bp_rs232_2line_iob is
43begin
44
45 IOB_RXD : iob_reg_i -- line idle=1, so init sync flop =1
46 generic map (INIT => '1')
47 port map (CLK => CLK, CE => '1', DI => RXD, PAD => I_RXD);
48
49 IOB_TXD : iob_reg_o -- line idle=1, so init sync flop =1
50 generic map (INIT => '1')
51 port map (CLK => CLK, CE => '1', DO => TXD, PAD => O_TXD);
52
53end syn;
std_logic slbit
Definition: slvtypes.vhd:30
Definition: xlib.vhd:35