w11 - vhd 0.794
W11 CPU core and support modules
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Generics | Libraries | Ports | Use Clauses
example_top Entity Reference
Inheritance diagram for example_top:
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Collaboration diagram for example_top:
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Entities

arch_example_top  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
numeric_std 

Generics

BL_WIDTH  integer := 10
PORT_MODE  string := " BI_MODE "
DATA_MODE  std_logic_vector ( 3 downto 0 ) := " 0010 "
TST_MEM_INSTR_MODE  string := " R_W_INSTR_MODE "
EYE_TEST  string := " FALSE "
DATA_PATTERN  string := " DGEN_ALL "
CMD_PATTERN  string := " CGEN_ALL "
BEGIN_ADDRESS  std_logic_vector ( 31 downto 0 ) := X " 00000000 "
END_ADDRESS  std_logic_vector ( 31 downto 0 ) := X " 00ffffff "
PRBS_EADDR_MASK_POS  std_logic_vector ( 31 downto 0 ) := X " ff000000 "
CMD_WDT  std_logic_vector ( 31 downto 0 ) := X " 000003ff "
WR_WDT  std_logic_vector ( 31 downto 0 ) := X " 00001fff "
RD_WDT  std_logic_vector ( 31 downto 0 ) := X " 000003ff "
COL_WIDTH  integer := 10
CS_WIDTH  integer := 1
DM_WIDTH  integer := 2
DQ_WIDTH  integer := 16
DQS_CNT_WIDTH  integer := 1
DRAM_WIDTH  integer := 8
ECC_TEST  string := " OFF "
RANKS  integer := 1
ROW_WIDTH  integer := 14
ADDR_WIDTH  integer := 28
BURST_MODE  string := " 8 "
SIMULATION  string := " FALSE "
TCQ  integer := 100
DRAM_TYPE  string := " DDR3 "
nCK_PER_CLK  integer := 4
DEBUG_PORT  string := " OFF "
TEMP_MON_CONTROL  string := " EXTERNAL "
RST_ACT_LOW  integer := 0
ADDR_MODE  std_logic_vector ( 3 downto 0 ) := " 0011 "
MEM_ADDR_ORDER  string := " ROW_BANK_COLUMN "
BANK_WIDTH  integer := 3
DQS_WIDTH  integer := 2

Ports

ddr3_dq   inout   std_logic_vector ( 15 downto 0 )
ddr3_dqs_p   inout   std_logic_vector ( 1 downto 0 )
ddr3_dqs_n   inout   std_logic_vector ( 1 downto 0 )
ddr3_addr   out   std_logic_vector ( 13 downto 0 )
ddr3_ba   out   std_logic_vector ( 2 downto 0 )
ddr3_ras_n   out   std_logic
ddr3_cas_n   out   std_logic
ddr3_we_n   out   std_logic
ddr3_reset_n   out   std_logic
ddr3_ck_p   out   std_logic_vector ( 0 downto 0 )
ddr3_ck_n   out   std_logic_vector ( 0 downto 0 )
ddr3_cke   out   std_logic_vector ( 0 downto 0 )
ddr3_cs_n   out   std_logic_vector ( 0 downto 0 )
ddr3_dm   out   std_logic_vector ( 1 downto 0 )
ddr3_odt   out   std_logic_vector ( 0 downto 0 )
sys_clk_i   in   std_logic
clk_ref_i   in   std_logic
tg_compare_error   out   std_logic
init_calib_complete   out   std_logic
device_temp_i   in   std_logic_vector ( 11 downto 0 )
sys_rst   in   std_logic
ddr2_dq   inout   std_logic_vector ( 15 downto 0 )
ddr2_dqs_p   inout   std_logic_vector ( 1 downto 0 )
ddr2_dqs_n   inout   std_logic_vector ( 1 downto 0 )
ddr2_addr   out   std_logic_vector ( 12 downto 0 )
ddr2_ba   out   std_logic_vector ( 2 downto 0 )
ddr2_ras_n   out   std_logic
ddr2_cas_n   out   std_logic
ddr2_we_n   out   std_logic
ddr2_ck_p   out   std_logic_vector ( 0 downto 0 )
ddr2_ck_n   out   std_logic_vector ( 0 downto 0 )
ddr2_cke   out   std_logic_vector ( 0 downto 0 )
ddr2_cs_n   out   std_logic_vector ( 0 downto 0 )
ddr2_dm   out   std_logic_vector ( 1 downto 0 )
ddr2_odt   out   std_logic_vector ( 0 downto 0 )

Detailed Description

Definition at line 77 of file example_top.vhd.

Member Data Documentation

◆ BL_WIDTH

BL_WIDTH integer := 10
Generic

Definition at line 82 of file example_top.vhd.

◆ PORT_MODE

PORT_MODE string := " BI_MODE "
Generic

Definition at line 83 of file example_top.vhd.

◆ DATA_MODE

DATA_MODE std_logic_vector ( 3 downto 0 ) := " 0010 "
Generic

Definition at line 84 of file example_top.vhd.

◆ TST_MEM_INSTR_MODE

TST_MEM_INSTR_MODE string := " R_W_INSTR_MODE "
Generic

Definition at line 85 of file example_top.vhd.

◆ EYE_TEST

EYE_TEST string := " FALSE "
Generic

Definition at line 86 of file example_top.vhd.

◆ DATA_PATTERN

DATA_PATTERN string := " DGEN_ALL "
Generic

Definition at line 91 of file example_top.vhd.

◆ CMD_PATTERN

CMD_PATTERN string := " CGEN_ALL "
Generic

Definition at line 97 of file example_top.vhd.

◆ BEGIN_ADDRESS

BEGIN_ADDRESS std_logic_vector ( 31 downto 0 ) := X " 00000000 "
Generic

Definition at line 100 of file example_top.vhd.

◆ END_ADDRESS

END_ADDRESS std_logic_vector ( 31 downto 0 ) := X " 00ffffff "
Generic

Definition at line 101 of file example_top.vhd.

◆ PRBS_EADDR_MASK_POS

PRBS_EADDR_MASK_POS std_logic_vector ( 31 downto 0 ) := X " ff000000 "
Generic

Definition at line 102 of file example_top.vhd.

◆ CMD_WDT

CMD_WDT std_logic_vector ( 31 downto 0 ) := X " 000003ff "
Generic

Definition at line 103 of file example_top.vhd.

◆ WR_WDT

WR_WDT std_logic_vector ( 31 downto 0 ) := X " 00001fff "
Generic

Definition at line 104 of file example_top.vhd.

◆ RD_WDT

RD_WDT std_logic_vector ( 31 downto 0 ) := X " 000003ff "
Generic

Definition at line 105 of file example_top.vhd.

◆ COL_WIDTH

COL_WIDTH integer := 10
Generic

Definition at line 109 of file example_top.vhd.

◆ CS_WIDTH

CS_WIDTH integer := 1
Generic

Definition at line 111 of file example_top.vhd.

◆ DM_WIDTH

DM_WIDTH integer := 2
Generic

Definition at line 113 of file example_top.vhd.

◆ DQ_WIDTH

DQ_WIDTH integer := 16
Generic

Definition at line 115 of file example_top.vhd.

◆ DQS_CNT_WIDTH

DQS_CNT_WIDTH integer := 1
Generic

Definition at line 117 of file example_top.vhd.

◆ DRAM_WIDTH

DRAM_WIDTH integer := 8
Generic

Definition at line 119 of file example_top.vhd.

◆ ECC_TEST

ECC_TEST string := " OFF "
Generic

Definition at line 121 of file example_top.vhd.

◆ RANKS

RANKS integer := 1
Generic

Definition at line 122 of file example_top.vhd.

◆ ROW_WIDTH

ROW_WIDTH integer := 14
Generic

Definition at line 124 of file example_top.vhd.

◆ ADDR_WIDTH

ADDR_WIDTH integer := 28
Generic

Definition at line 126 of file example_top.vhd.

◆ BURST_MODE

BURST_MODE string := " 8 "
Generic

Definition at line 134 of file example_top.vhd.

◆ SIMULATION

SIMULATION string := " FALSE "
Generic

Definition at line 145 of file example_top.vhd.

◆ TCQ

TCQ integer := 100
Generic

Definition at line 152 of file example_top.vhd.

◆ DRAM_TYPE

DRAM_TYPE string := " DDR3 "
Generic

Definition at line 154 of file example_top.vhd.

◆ nCK_PER_CLK

nCK_PER_CLK integer := 4
Generic

Definition at line 160 of file example_top.vhd.

◆ DEBUG_PORT

DEBUG_PORT string := " OFF "
Generic

Definition at line 166 of file example_top.vhd.

◆ TEMP_MON_CONTROL

TEMP_MON_CONTROL string := " EXTERNAL "
Generic

Definition at line 173 of file example_top.vhd.

◆ RST_ACT_LOW

RST_ACT_LOW integer := 0
Generic

Definition at line 179 of file example_top.vhd.

◆ ddr3_dq

ddr3_dq inout std_logic_vector ( 15 downto 0 )
Port

Definition at line 183 of file example_top.vhd.

◆ ddr3_dqs_p

ddr3_dqs_p inout std_logic_vector ( 1 downto 0 )
Port

Definition at line 184 of file example_top.vhd.

◆ ddr3_dqs_n

ddr3_dqs_n inout std_logic_vector ( 1 downto 0 )
Port

Definition at line 185 of file example_top.vhd.

◆ ddr3_addr

ddr3_addr out std_logic_vector ( 13 downto 0 )
Port

Definition at line 188 of file example_top.vhd.

◆ ddr3_ba

ddr3_ba out std_logic_vector ( 2 downto 0 )
Port

Definition at line 189 of file example_top.vhd.

◆ ddr3_ras_n

ddr3_ras_n out std_logic
Port

Definition at line 190 of file example_top.vhd.

◆ ddr3_cas_n

ddr3_cas_n out std_logic
Port

Definition at line 191 of file example_top.vhd.

◆ ddr3_we_n

ddr3_we_n out std_logic
Port

Definition at line 192 of file example_top.vhd.

◆ ddr3_reset_n

ddr3_reset_n out std_logic
Port

Definition at line 193 of file example_top.vhd.

◆ ddr3_ck_p

ddr3_ck_p out std_logic_vector ( 0 downto 0 )
Port

Definition at line 194 of file example_top.vhd.

◆ ddr3_ck_n

ddr3_ck_n out std_logic_vector ( 0 downto 0 )
Port

Definition at line 195 of file example_top.vhd.

◆ ddr3_cke

ddr3_cke out std_logic_vector ( 0 downto 0 )
Port

Definition at line 196 of file example_top.vhd.

◆ ddr3_cs_n

ddr3_cs_n out std_logic_vector ( 0 downto 0 )
Port

Definition at line 197 of file example_top.vhd.

◆ ddr3_dm

ddr3_dm out std_logic_vector ( 1 downto 0 )
Port

Definition at line 198 of file example_top.vhd.

◆ ddr3_odt

ddr3_odt out std_logic_vector ( 0 downto 0 )
Port

Definition at line 199 of file example_top.vhd.

◆ sys_clk_i

sys_clk_i in std_logic
Port

Definition at line 203 of file example_top.vhd.

◆ clk_ref_i

clk_ref_i in std_logic
Port

Definition at line 205 of file example_top.vhd.

◆ tg_compare_error

tg_compare_error out std_logic
Port

Definition at line 207 of file example_top.vhd.

◆ init_calib_complete

init_calib_complete out std_logic
Port

Definition at line 208 of file example_top.vhd.

◆ device_temp_i

device_temp_i in std_logic_vector ( 11 downto 0 )
Port

Definition at line 209 of file example_top.vhd.

◆ sys_rst

sys_rst in std_logic
Port

Definition at line 219 of file example_top.vhd.

◆ ieee

ieee
Library

Definition at line 72 of file example_top.vhd.

◆ std_logic_1164

std_logic_1164
use clause

Definition at line 73 of file example_top.vhd.

◆ numeric_std

numeric_std
use clause

Definition at line 74 of file example_top.vhd.

◆ ADDR_MODE

ADDR_MODE std_logic_vector ( 3 downto 0 ) := " 0011 "
Generic

Definition at line 86 of file example_top.vhd.

◆ MEM_ADDR_ORDER

MEM_ADDR_ORDER string := " ROW_BANK_COLUMN "
Generic

Definition at line 104 of file example_top.vhd.

◆ BANK_WIDTH

BANK_WIDTH integer := 3
Generic

Definition at line 120 of file example_top.vhd.

◆ DQS_WIDTH

DQS_WIDTH integer := 2
Generic

Definition at line 128 of file example_top.vhd.

◆ ddr2_dq

ddr2_dq inout std_logic_vector ( 15 downto 0 )
Port

Definition at line 194 of file example_top.vhd.

◆ ddr2_dqs_p

ddr2_dqs_p inout std_logic_vector ( 1 downto 0 )
Port

Definition at line 195 of file example_top.vhd.

◆ ddr2_dqs_n

ddr2_dqs_n inout std_logic_vector ( 1 downto 0 )
Port

Definition at line 196 of file example_top.vhd.

◆ ddr2_addr

ddr2_addr out std_logic_vector ( 12 downto 0 )
Port

Definition at line 199 of file example_top.vhd.

◆ ddr2_ba

ddr2_ba out std_logic_vector ( 2 downto 0 )
Port

Definition at line 200 of file example_top.vhd.

◆ ddr2_ras_n

ddr2_ras_n out std_logic
Port

Definition at line 201 of file example_top.vhd.

◆ ddr2_cas_n

ddr2_cas_n out std_logic
Port

Definition at line 202 of file example_top.vhd.

◆ ddr2_we_n

ddr2_we_n out std_logic
Port

Definition at line 203 of file example_top.vhd.

◆ ddr2_ck_p

ddr2_ck_p out std_logic_vector ( 0 downto 0 )
Port

Definition at line 204 of file example_top.vhd.

◆ ddr2_ck_n

ddr2_ck_n out std_logic_vector ( 0 downto 0 )
Port

Definition at line 205 of file example_top.vhd.

◆ ddr2_cke

ddr2_cke out std_logic_vector ( 0 downto 0 )
Port

Definition at line 206 of file example_top.vhd.

◆ ddr2_cs_n

ddr2_cs_n out std_logic_vector ( 0 downto 0 )
Port

Definition at line 207 of file example_top.vhd.

◆ ddr2_dm

ddr2_dm out std_logic_vector ( 1 downto 0 )
Port

Definition at line 208 of file example_top.vhd.

◆ ddr2_odt

ddr2_odt out std_logic_vector ( 0 downto 0 )
Port

Definition at line 209 of file example_top.vhd.

The documentation for this design unit was generated from the following files: