w11 - vhd 0.794
W11 CPU core and support modules
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Constants | Instantiations | Processes | Records | Signals | Subtypes | Types
sim Architecture Reference
Architecture >> sim

Processes

proc_regs  ( CLK )
proc_next  ( R_REGS , APP_EN , APP_ADDR , APP_CMD , APP_WDF_WREN , APP_WDF_END , APP_REF_REQ , APP_ZQ_REQ , R_MEMDO )
proc_mem  ( CLK )
proc_moni  ( CLK )

Constants

mwidth  positive := 2 ** BAWIDTH
dwidth  positive := 8 * mwidth
colwidth  positive := 11
rowwidth  positive := MAWIDTH - colwidth
memsize  positive := 2 ** SAWIDTH
datzero  bv8 := ( others = > ' 0 ' )
c_rdwait_rhit  positive := 2
c_rdwait_rmis  positive := 5
c_wrwait_rhit  positive := 2
c_wrwait_rmis  positive := 5
c_wrwait_max  positive := c_wrwait_rmis
c_refwait  positive := 10
c_zqwait  positive := 8
c_crdy_init  slv13 := " 0001111110111 "
rowaddr_init  slv ( rowwidth - 1 downto 0 ) := ( others = > ' 1 ' )
regs_init  regs_type := ( CACO_WAIT , ' 0 ' , ' 0 ' , rowaddr_init , 0 , 0 , c_crdy_init , 0 , 0 )

Types

ram_type  ( 0 to memsize - 1 ) bv8

Subtypes

addr_f_row  integer range MAWIDTH - 1 downto colwidth
bv8  bit_vector ( 7 downto 0 )

Signals

CLK  slbit
R_REGS  regs_type := regs_init
N_REGS  regs_type
CLKFX  slbit
MEM_EN  slbit := ' 0 '
MEM_WE  slbit := ' 0 '
MEM_ADDR  slv ( SAWIDTH - BAWIDTH - 1 downto 0 )
R_MEMDO  slv ( dwidth - 1 downto 0 ) := ( others = > ' 0 ' )

Records

regs_type 
cacowait natural
enacaco slbit
enardy slbit
rowaddr slv ( rowwidth - 1 downto 0 )
rdwait natural
wrwait natural
crdypat slv13
refwait natural
zqwait natural

Instantiations

uiclkgen  sfs_gsim_core <Entity sfs_gsim_core>

Detailed Description

Definition at line 63 of file migui_core_gsim.vhd.

Member Function/Procedure/Process Documentation

◆ proc_regs()

proc_regs (   CLK)

Definition at line 148 of file migui_core_gsim.vhd.

◆ proc_next()

proc_next (   R_REGS ,
  APP_EN ,
  APP_ADDR ,
  APP_CMD ,
  APP_WDF_WREN ,
  APP_WDF_END ,
  APP_REF_REQ ,
  APP_ZQ_REQ ,
  R_MEMDO  
)
Process

Definition at line 161 of file migui_core_gsim.vhd.

◆ proc_mem()

proc_mem (   CLK  
)
Process

Definition at line 294 of file migui_core_gsim.vhd.

◆ proc_moni()

proc_moni (   CLK  
)
Process

Definition at line 319 of file migui_core_gsim.vhd.

Member Data Documentation

◆ mwidth

mwidth positive := 2 ** BAWIDTH
Constant

Definition at line 65 of file migui_core_gsim.vhd.

◆ dwidth

dwidth positive := 8 * mwidth
Constant

Definition at line 66 of file migui_core_gsim.vhd.

◆ colwidth

colwidth positive := 11
Constant

Definition at line 70 of file migui_core_gsim.vhd.

◆ rowwidth

rowwidth positive := MAWIDTH - colwidth
Constant

Definition at line 71 of file migui_core_gsim.vhd.

◆ addr_f_row

addr_f_row integer range MAWIDTH - 1 downto colwidth
Subtype

Definition at line 72 of file migui_core_gsim.vhd.

◆ bv8

bv8 bit_vector ( 7 downto 0 )
Subtype

Definition at line 74 of file migui_core_gsim.vhd.

◆ memsize

memsize positive := 2 ** SAWIDTH
Constant

Definition at line 75 of file migui_core_gsim.vhd.

◆ datzero

datzero bv8 := ( others = > ' 0 ' )
Constant

Definition at line 76 of file migui_core_gsim.vhd.

◆ ram_type

ram_type ( 0 to memsize - 1 ) bv8
Type

Definition at line 77 of file migui_core_gsim.vhd.

◆ c_rdwait_rhit

c_rdwait_rhit positive := 2
Constant

Definition at line 80 of file migui_core_gsim.vhd.

◆ c_rdwait_rmis

c_rdwait_rmis positive := 5
Constant

Definition at line 81 of file migui_core_gsim.vhd.

◆ c_wrwait_rhit

c_wrwait_rhit positive := 2
Constant

Definition at line 82 of file migui_core_gsim.vhd.

◆ c_wrwait_rmis

c_wrwait_rmis positive := 5
Constant

Definition at line 83 of file migui_core_gsim.vhd.

◆ c_wrwait_max

c_wrwait_max positive := c_wrwait_rmis
Constant

Definition at line 84 of file migui_core_gsim.vhd.

◆ c_refwait

c_refwait positive := 10
Constant

Definition at line 86 of file migui_core_gsim.vhd.

◆ c_zqwait

c_zqwait positive := 8
Constant

Definition at line 87 of file migui_core_gsim.vhd.

◆ c_crdy_init

c_crdy_init slv13 := " 0001111110111 "
Constant

Definition at line 90 of file migui_core_gsim.vhd.

◆ regs_type

regs_type
Record

Definition at line 92 of file migui_core_gsim.vhd.

◆ cacowait

cacowait natural
Record

Definition at line 93 of file migui_core_gsim.vhd.

◆ enacaco

enacaco slbit
Record

Definition at line 94 of file migui_core_gsim.vhd.

◆ enardy

enardy slbit
Record

Definition at line 95 of file migui_core_gsim.vhd.

◆ rowaddr

rowaddr slv ( rowwidth - 1 downto 0 )
Record

Definition at line 96 of file migui_core_gsim.vhd.

◆ rdwait

rdwait natural
Record

Definition at line 97 of file migui_core_gsim.vhd.

◆ wrwait

wrwait natural
Record

Definition at line 98 of file migui_core_gsim.vhd.

◆ crdypat

crdypat slv13
Record

Definition at line 99 of file migui_core_gsim.vhd.

◆ refwait

refwait natural
Record

Definition at line 100 of file migui_core_gsim.vhd.

◆ zqwait

zqwait natural
Record

Definition at line 101 of file migui_core_gsim.vhd.

◆ rowaddr_init

rowaddr_init slv ( rowwidth - 1 downto 0 ) := ( others = > ' 1 ' )
Constant

Definition at line 104 of file migui_core_gsim.vhd.

◆ regs_init

regs_init regs_type := ( CACO_WAIT , ' 0 ' , ' 0 ' , rowaddr_init , 0 , 0 , c_crdy_init , 0 , 0 )
Constant

Definition at line 106 of file migui_core_gsim.vhd.

◆ CLK

CLK slbit
Signal

Definition at line 114 of file migui_core_gsim.vhd.

◆ R_REGS

R_REGS regs_type := regs_init
Signal

Definition at line 116 of file migui_core_gsim.vhd.

◆ N_REGS

N_REGS regs_type
Signal

Definition at line 117 of file migui_core_gsim.vhd.

◆ CLKFX

CLKFX slbit
Signal

Definition at line 119 of file migui_core_gsim.vhd.

◆ MEM_EN

MEM_EN slbit := ' 0 '
Signal

Definition at line 121 of file migui_core_gsim.vhd.

◆ MEM_WE

MEM_WE slbit := ' 0 '
Signal

Definition at line 122 of file migui_core_gsim.vhd.

◆ MEM_ADDR

MEM_ADDR slv ( SAWIDTH - BAWIDTH - 1 downto 0 )
Signal

Definition at line 123 of file migui_core_gsim.vhd.

◆ R_MEMDO

R_MEMDO slv ( dwidth - 1 downto 0 ) := ( others = > ' 0 ' )
Signal

Definition at line 124 of file migui_core_gsim.vhd.

◆ uiclkgen

uiclkgen sfs_gsim_core
Instantiation

Definition at line 142 of file migui_core_gsim.vhd.

The documentation for this design unit was generated from the following file: