22use ieee.std_logic_1164.
all;
23use ieee.numeric_std.
all;
74 subtype bv8 is bit_vector(7 downto 0);
130 report "assert( BAWIDTH = 3 or 4 )"
151 if rising_edge(CLK) then
159 end process proc_regs;
168 variable iappcrdy : slbit := '0';
169 variable iappwrdy : slbit := '0';
170 variable iapprefack : slbit := '0';
171 variable iappzqack : slbit := '0';
172 variable imemen : slbit := '0';
173 variable imemwe : slbit := '0';
174 variable irdval : slbit := '0';
189 n.crdypat := r.crdypat(11 downto 0) & r.crdypat(12);
192 if r.cacowait > 0 then
193 n.cacowait := r.cacowait - 1;
197 if r.cacowait = 1 then
206 elsif r.rdwait > 0 then
208 elsif r.enardy='0' or r.crdypat(0)='0' then
213 if APP_CMD = c_migui_cmd_read then
221 elsif APP_CMD = c_migui_cmd_write then
236 if r.enacaco = '1' then
238 n.wrwait := r.wrwait - 1;
241 n.rdwait := r.rdwait - 1;
253 if r.refwait > 0 then
254 n.refwait := r.refwait -1;
255 if r.refwait = 1 then
266 n.zqwait := r.zqwait -1;
292 end process proc_next;
296 variable membase : integer := 0;
298 if rising_edge(CLK) then
303 for i in 0 to mwidth-1 loop
311 for i in 0 to mwidth-1 loop
312 R_MEMDO(8*i+7 downto 8*i) <= to_stdlogicvector(ram(membase + i));
317 end process proc_mem;
321 if rising_edge(CLK) then
324 assert APP_CMD = c_migui_cmd_read or
326 report "migui_core_gsim: FAIL: APP_CMD not 000 or 001"
330 report "migui_core_gsim: FAIL: out of sim-memory size access"
336 report "migui_core_gsim: FAIL: APP_WDF_(END,WREN) missed on write"
340 report "migui_core_gsim: FAIL: spurious APP_WDF_(END,WREN)"
345 end process proc_moni;
( 0 to memsize- 1) bv8 ram_type
positive := MAWIDTH- colwidth rowwidth
bv8 :=( others => '0') datzero
slv( dwidth- 1 downto 0) :=( others => '0') R_MEMDO
positive := 8* mwidth dwidth
positive := 2** BAWIDTH mwidth
positive := 5 c_rdwait_rmis
slv( SAWIDTH- BAWIDTH- 1 downto 0) MEM_ADDR
slv( rowwidth- 1 downto 0) :=( others => '1') rowaddr_init
regs_type :=( CACO_WAIT, '0', '0', rowaddr_init, 0, 0, c_crdy_init, 0, 0) regs_init
slv13 := "0001111110111" c_crdy_init
integer range MAWIDTH- 1 downto colwidth addr_f_row
regs_type := regs_init R_REGS
positive := c_wrwait_rmis c_wrwait_max
positive := 2 c_wrwait_rhit
positive := 2** SAWIDTH memsize
bit_vector( 7 downto 0) bv8
positive := 2 c_rdwait_rhit
positive := 5 c_wrwait_rmis
out APP_RD_DATA_VALID slbit
out APP_RD_DATA_END slbit
in APP_WDF_MASK slv(( 2** BAWIDTH)- 1 downto 0)
in APP_WDF_DATA slv( 8*( 2** BAWIDTH)- 1 downto 0)
out INIT_CALIB_COMPLETE slbit
out APP_RD_DATA slv( 8*( 2** BAWIDTH)- 1 downto 0)
CLKMUI_DIV positive := 12
in APP_ADDR slv( MAWIDTH- 1 downto 0)
out UI_CLK_SYNC_RST slbit
std_logic_vector( 12 downto 0) slv13
std_logic_vector( 2 downto 0) slv3