w11 - vhd 0.794
W11 CPU core and support modules
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dcm_sfs_gsim.vhd
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1-- $Id: dcm_sfs_gsim.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2010-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: dcm_sfs - sim
7-- Description: DCM for simple frequency synthesis
8-- simple vhdl model, without Xilinx UNISIM primitives
9--
10-- Dependencies: -
11-- Test bench: -
12-- Target Devices: generic Spartan-3A,-3E
13-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.34
14--
15-- Revision History:
16-- Date Rev Version Comment
17-- 2018-11-03 1065 1.1 use sfs_gsim_core
18-- 2011-11-17 426 1.0.1 rename dcm_sp_sfs -> dcm_sfs
19-- 2010-11-12 338 1.0 Initial version
20------------------------------------------------------------------------------
21
22library ieee;
23use ieee.std_logic_1164.all;
24
25use work.slvtypes.all;
26use work.xlib.all;
27
28entity dcm_sfs is -- DCM for simple frequency synthesis
29 generic (
30 CLKFX_DIVIDE : positive := 1; -- FX clock divide (1-32)
31 CLKFX_MULTIPLY : positive := 1; -- FX clock multiply (2-32) (1->no DCM)
32 CLKIN_PERIOD : real := 20.0); -- CLKIN period (def is 20.0 ns)
33 port (
34 CLKIN : in slbit; -- clock input
35 CLKFX : out slbit; -- clock output (synthesized freq.)
36 LOCKED : out slbit -- dcm locked
37 );
38end dcm_sfs;
39
40
41architecture sim of dcm_sfs is
42begin
43
44 -- generate clock
45 SFS: sfs_gsim_core
46 generic map (
47 VCO_DIVIDE => 1,
50 port map (
51 CLKIN => CLKIN,
52 CLKFX => CLKFX,
53 LOCKED => LOCKED
54 );
55
56end sim;
CLKFX_DIVIDE positive := 1
in CLKIN slbit
CLKFX_MULTIPLY positive := 1
out LOCKED slbit
CLKIN_PERIOD real := 20.0
out CLKFX slbit
VCO_DIVIDE positive := 1
OUT_DIVIDE positive := 1
in CLKIN slbit
VCO_MULTIPLY positive := 1
out LOCKED slbit
out CLKFX slbit
std_logic slbit
Definition: slvtypes.vhd:30
Definition: xlib.vhd:35