w11 - vhd 0.794
W11 CPU core and support modules
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fifo_1c_dram_raw.vhd
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1-- $Id: fifo_1c_dram_raw.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: fifo_1c_dram_raw - syn
7-- Description: FIFO, single clock domain, distributed RAM based, 'raw'
8-- interface exposing dram signals.
9--
10-- Dependencies: ram_1swar_1ar_gen
11--
12-- Test bench: tb/tb_fifo_1c_dram
13-- Target Devices: generic Spartan, Virtex
14-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
15-- Revision History:
16-- Date Rev Version Comment
17-- 2011-11-07 421 1.0.2 now numeric_std clean
18-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
19-- 2007-06-03 47 1.0 Initial version
20------------------------------------------------------------------------------
21
22library ieee;
23use ieee.std_logic_1164.all;
24use ieee.numeric_std.all;
25
26use work.slvtypes.all;
27use work.memlib.all;
28
29entity fifo_1c_dram_raw is -- fifo, 1 clock, dram based, raw
30 generic (
31 AWIDTH : positive := 4; -- address width (sets size)
32 DWIDTH : positive := 16); -- data width
33 port (
34 CLK : in slbit; -- clock
35 RESET : in slbit; -- reset
36 WE : in slbit; -- write enable
37 RE : in slbit; -- read enable
38 DI : in slv(DWIDTH-1 downto 0); -- input data
39 DO : out slv(DWIDTH-1 downto 0); -- output data
40 SIZE : out slv(AWIDTH-1 downto 0); -- number of used slots
41 EMPTY : out slbit; -- empty flag
42 FULL : out slbit -- full flag
43 );
45
46
47architecture syn of fifo_1c_dram_raw is
48
49 type regs_type is record
50 waddr : slv(AWIDTH-1 downto 0); -- write address
51 raddr : slv(AWIDTH-1 downto 0); -- read address
52 empty : slbit; -- empty flag
53 full : slbit; -- full flag
54 end record regs_type;
55
56 constant memsize : positive := 2**AWIDTH;
57 constant regs_init : regs_type := (
58 slv(to_unsigned(0,AWIDTH)), -- waddr
59 slv(to_unsigned(0,AWIDTH)), -- raddr
60 '1','0' -- empty,full
61 );
62
63 signal R_REGS : regs_type := regs_init; -- state registers
64 signal N_REGS : regs_type := regs_init; -- next value state regs
65
66 signal RAM_WE : slbit := '0';
67
68begin
69
71 generic map (
72 AWIDTH => AWIDTH,
73 DWIDTH => DWIDTH)
74 port map (
75 CLK => CLK,
76 WE => RAM_WE,
77 ADDRA => R_REGS.waddr,
78 ADDRB => R_REGS.raddr,
79 DI => DI,
80 DOA => open,
81 DOB => DO
82 );
83
84 proc_regs: process (CLK)
85 begin
86
87 if rising_edge(CLK) then
88 R_REGS <= N_REGS;
89 end if;
90
91 end process proc_regs;
92
93 proc_next: process (R_REGS, RESET, WE, RE)
94
95 variable r : regs_type := regs_init;
96 variable n : regs_type := regs_init;
97
98 variable isize : slv(AWIDTH-1 downto 0) := (others=>'0');
99
100 variable we_val : slbit := '0';
101 variable re_val : slbit := '0';
102 variable iram_we : slbit := '0';
103
104 begin
105
106 r := R_REGS;
107 n := R_REGS;
108
109 re_val := RE and not r.empty;
110 we_val := WE and ((not r.full) or RE);
111 isize := slv(unsigned(r.waddr) - unsigned(r.raddr));
112 iram_we := '0';
113
114 if RESET = '1' then
115 n := regs_init;
116
117 else
118
119 if we_val = '1' then
120 n.waddr := slv(unsigned(r.waddr) + 1);
121 iram_we := '1';
122 if re_val = '0' then
123 n.empty := '0';
124 if unsigned(isize) = memsize-1 then
125 n.full := '1';
126 end if;
127 end if;
128 end if;
129
130 if re_val = '1' then
131 n.raddr := slv(unsigned(r.raddr) + 1);
132 if we_val = '0' then
133 n.full := '0';
134 if unsigned(isize) = 1 then
135 n.empty := '1';
136 end if;
137 end if;
138 end if;
139
140 end if;
141
142 N_REGS <= n;
143
144 RAM_WE <= iram_we;
145
146 SIZE <= isize;
147 EMPTY <= r.empty;
148 FULL <= r.full;
149
150 end process proc_next;
151
152end syn;
regs_type := regs_init N_REGS
positive := 2** AWIDTH memsize
regs_type := regs_init R_REGS
regs_type :=( slv( to_unsigned( 0, AWIDTH) ), slv( to_unsigned( 0, AWIDTH) ), '1', '0') regs_init
out DO slv( DWIDTH- 1 downto 0)
AWIDTH positive := 4
in DI slv( DWIDTH- 1 downto 0)
out SIZE slv( AWIDTH- 1 downto 0)
DWIDTH positive := 16
AWIDTH positive := 4
in DI slv( DWIDTH- 1 downto 0)
in ADDRB slv( AWIDTH- 1 downto 0)
in ADDRA slv( AWIDTH- 1 downto 0)
out DOB slv( DWIDTH- 1 downto 0)
out DOA slv( DWIDTH- 1 downto 0)
DWIDTH positive := 16
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector slv
Definition: slvtypes.vhd:31