23use ieee.std_logic_1164.
all;
24use ieee.numeric_std.
all;
77 ADDRA => R_REGS.waddr,
78 ADDRB => R_REGS.raddr,
84 proc_regs:
process (
CLK)
87 if rising_edge(CLK) then
91 end process proc_regs;
98 variable isize : slv(AWIDTH-1 downto 0) := (others=>'0');
100 variable we_val : slbit := '0';
101 variable re_val : slbit := '0';
102 variable iram_we : slbit := '0';
109 re_val := RE and not r.empty;
110 we_val := WE and ((not r.full) or RE);
111 isize := slv(unsigned(r.waddr) - unsigned(r.raddr));
120 n.waddr := slv(unsigned(r.waddr) + 1);
124 if unsigned(isize) = memsize-1 then
131 n.raddr := slv(unsigned(r.raddr) + 1);
134 if unsigned(isize) = 1 then
150 end process proc_next;
regs_type := regs_init N_REGS
positive := 2** AWIDTH memsize
regs_type := regs_init R_REGS
regs_type :=( slv( to_unsigned( 0, AWIDTH) ), slv( to_unsigned( 0, AWIDTH) ), '1', '0') regs_init
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)
out SIZE slv( AWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)
in ADDRB slv( AWIDTH- 1 downto 0)
in ADDRA slv( AWIDTH- 1 downto 0)
out DOB slv( DWIDTH- 1 downto 0)
out DOA slv( DWIDTH- 1 downto 0)