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W11 CPU core and support modules
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memlib.vhd
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1-- $Id: memlib.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2006-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Package Name: memlib
7-- Description: Basic memory components: single/dual port synchronous and
8-- asynchronus rams; Fifo's.
9--
10-- Dependencies: -
11-- Tool versions: ise 8.2-14.7; viv 2014.4-2018.3; ghdl 0.18-0.35
12-- Revision History:
13-- Date Rev Version Comment
14-- 2019-02-03 1109 1.1.1 add fifo_simple_dram
15-- 2016-03-25 751 1.1 add fifo_2c_dram2
16-- 2008-03-08 123 1.0.3 add ram_2swsr_xfirst_gen_unisim
17-- 2008-03-02 122 1.0.2 change generic default for BRAM models
18-- 2007-12-27 106 1.0.1 add fifo_2c_dram
19-- 2007-06-03 45 1.0 Initial version
20------------------------------------------------------------------------------
21
22library ieee;
23use ieee.std_logic_1164.all;
24
25use work.slvtypes.all;
26
27package memlib is
28
29component ram_1swar_gen is -- RAM, 1 sync w asyn r port
30 generic (
31 AWIDTH : positive := 4; -- address port width
32 DWIDTH : positive := 16); -- data port width
33 port (
34 CLK : in slbit; -- clock
35 WE : in slbit; -- write enable
36 ADDR : in slv(AWIDTH-1 downto 0); -- address port
37 DI : in slv(DWIDTH-1 downto 0); -- data in port
38 DO : out slv(DWIDTH-1 downto 0) -- data out port
39 );
40end component;
41
42component ram_1swar_1ar_gen is -- RAM, 1 sync w asyn r + 1 asyn r port
43 generic (
44 AWIDTH : positive := 4; -- address port width
45 DWIDTH : positive := 16); -- data port width
46 port (
47 CLK : in slbit; -- clock
48 WE : in slbit; -- write enable (port A)
49 ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
50 ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
51 DI : in slv(DWIDTH-1 downto 0); -- data in (port A)
52 DOA : out slv(DWIDTH-1 downto 0); -- data out port A
53 DOB : out slv(DWIDTH-1 downto 0) -- data out port B
54 );
55end component;
56
57component ram_1swsr_wfirst_gen is -- RAM, 1 sync r/w ports, write first
58 generic (
59 AWIDTH : positive := 10; -- address port width
60 DWIDTH : positive := 16); -- data port width
61 port(
62 CLK : in slbit; -- clock
63 EN : in slbit; -- enable
64 WE : in slbit; -- write enable
65 ADDR : in slv(AWIDTH-1 downto 0); -- address port
66 DI : in slv(DWIDTH-1 downto 0); -- data in port
67 DO : out slv(DWIDTH-1 downto 0) -- data out port
68 );
69end component;
70
71component ram_1swsr_rfirst_gen is -- RAM, 1 sync r/w ports, read first
72 generic (
73 AWIDTH : positive := 11; -- address port width
74 DWIDTH : positive := 9); -- data port width
75 port(
76 CLK : in slbit; -- clock
77 EN : in slbit; -- enable
78 WE : in slbit; -- write enable
79 ADDR : in slv(AWIDTH-1 downto 0); -- address port
80 DI : in slv(DWIDTH-1 downto 0); -- data in port
81 DO : out slv(DWIDTH-1 downto 0) -- data out port
82 );
83end component;
84
85component ram_2swsr_wfirst_gen is -- RAM, 2 sync r/w ports, write first
86 generic (
87 AWIDTH : positive := 11; -- address port width
88 DWIDTH : positive := 9); -- data port width
89 port(
90 CLKA : in slbit; -- clock port A
91 CLKB : in slbit; -- clock port B
92 ENA : in slbit; -- enable port A
93 ENB : in slbit; -- enable port B
94 WEA : in slbit; -- write enable port A
95 WEB : in slbit; -- write enable port B
96 ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
97 ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
98 DIA : in slv(DWIDTH-1 downto 0); -- data in port A
99 DIB : in slv(DWIDTH-1 downto 0); -- data in port B
100 DOA : out slv(DWIDTH-1 downto 0); -- data out port A
101 DOB : out slv(DWIDTH-1 downto 0) -- data out port B
102 );
103end component;
104
105component ram_2swsr_rfirst_gen is -- RAM, 2 sync r/w ports, read first
106 generic (
107 AWIDTH : positive := 11; -- address port width
108 DWIDTH : positive := 9); -- data port width
109 port(
110 CLKA : in slbit; -- clock port A
111 CLKB : in slbit; -- clock port B
112 ENA : in slbit; -- enable port A
113 ENB : in slbit; -- enable port B
114 WEA : in slbit; -- write enable port A
115 WEB : in slbit; -- write enable port B
116 ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
117 ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
118 DIA : in slv(DWIDTH-1 downto 0); -- data in port A
119 DIB : in slv(DWIDTH-1 downto 0); -- data in port B
120 DOA : out slv(DWIDTH-1 downto 0); -- data out port A
121 DOB : out slv(DWIDTH-1 downto 0) -- data out port B
122 );
123end component;
124
125component ram_1swsr_xfirst_gen_unisim is -- RAM, 1 sync r/w port
126 generic (
127 AWIDTH : positive := 11; -- address port width
128 DWIDTH : positive := 9; -- data port width
129 WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST
130 port(
131 CLK : in slbit; -- clock
132 EN : in slbit; -- enable
133 WE : in slbit; -- write enable
134 ADDR : in slv(AWIDTH-1 downto 0); -- address
135 DI : in slv(DWIDTH-1 downto 0); -- data in
136 DO : out slv(DWIDTH-1 downto 0) -- data out
137 );
138end component;
139
140component ram_2swsr_xfirst_gen_unisim is -- RAM, 2 sync r/w ports
141 generic (
142 AWIDTH : positive := 11; -- address port width
143 DWIDTH : positive := 9; -- data port width
144 WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST
145 port(
146 CLKA : in slbit; -- clock port A
147 CLKB : in slbit; -- clock port B
148 ENA : in slbit; -- enable port A
149 ENB : in slbit; -- enable port B
150 WEA : in slbit; -- write enable port A
151 WEB : in slbit; -- write enable port B
152 ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
153 ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
154 DIA : in slv(DWIDTH-1 downto 0); -- data in port A
155 DIB : in slv(DWIDTH-1 downto 0); -- data in port B
156 DOA : out slv(DWIDTH-1 downto 0); -- data out port A
157 DOB : out slv(DWIDTH-1 downto 0) -- data out port B
158 );
159end component;
160
161component fifo_simple_dram is -- fifo, CE/WE interface, dram based
162 generic (
163 AWIDTH : positive := 6; -- address width (sets size)
164 DWIDTH : positive := 16); -- data width
165 port (
166 CLK : in slbit; -- clock
167 RESET : in slbit; -- reset
168 CE : in slbit; -- clock enable
169 WE : in slbit; -- write enable
170 DI : in slv(DWIDTH-1 downto 0); -- input data
171 DO : out slv(DWIDTH-1 downto 0); -- output data
172 EMPTY : out slbit; -- fifo empty status
173 FULL : out slbit; -- fifo full status
174 SIZE : out slv(AWIDTH-1 downto 0) -- number of used slots
175 );
176end component;
177
178component fifo_1c_dram_raw is -- fifo, 1 clock, dram based, raw
179 generic (
180 AWIDTH : positive := 4; -- address width (sets size)
181 DWIDTH : positive := 16); -- data width
182 port (
183 CLK : in slbit; -- clock
184 RESET : in slbit; -- reset
185 WE : in slbit; -- write enable
186 RE : in slbit; -- read enable
187 DI : in slv(DWIDTH-1 downto 0); -- input data
188 DO : out slv(DWIDTH-1 downto 0); -- output data
189 SIZE : out slv(AWIDTH-1 downto 0); -- number of used slots
190 EMPTY : out slbit; -- empty flag
191 FULL : out slbit -- full flag
192 );
193end component;
194
195component fifo_1c_dram is -- fifo, 1 clock, dram based
196 generic (
197 AWIDTH : positive := 4; -- address width (sets size)
198 DWIDTH : positive := 16); -- data width
199 port (
200 CLK : in slbit; -- clock
201 RESET : in slbit; -- reset
202 DI : in slv(DWIDTH-1 downto 0); -- input data
203 ENA : in slbit; -- write enable
204 BUSY : out slbit; -- write port hold
205 DO : out slv(DWIDTH-1 downto 0); -- output data
206 VAL : out slbit; -- read valid
207 HOLD : in slbit; -- read hold
208 SIZE : out slv(AWIDTH downto 0) -- number of used slots
209 );
210end component;
211
212component fifo_1c_bubble is -- fifo, 1 clock, bubble regs
213 generic (
214 NSTAGE : positive := 4; -- number of stages
215 DWIDTH : positive := 16); -- data width
216 port (
217 CLK : in slbit; -- clock
218 RESET : in slbit; -- reset
219 DI : in slv(DWIDTH-1 downto 0); -- input data
220 ENA : in slbit; -- write enable
221 BUSY : out slbit; -- write port hold
222 DO : out slv(DWIDTH-1 downto 0); -- output data
223 VAL : out slbit; -- read valid
224 HOLD : in slbit -- read hold
225 );
226end component;
227
228component fifo_2c_dram is -- fifo, 2 clock, dram based
229 generic (
230 AWIDTH : positive := 4; -- address width (sets size)
231 DWIDTH : positive := 16); -- data width
232 port (
233 CLKW : in slbit; -- clock (write side)
234 CLKR : in slbit; -- clock (read side)
235 RESETW : in slbit; -- W|reset from write side
236 RESETR : in slbit; -- R|reset from read side
237 DI : in slv(DWIDTH-1 downto 0); -- W|input data
238 ENA : in slbit; -- W|write enable
239 BUSY : out slbit; -- W|write port hold
240 DO : out slv(DWIDTH-1 downto 0); -- R|output data
241 VAL : out slbit; -- R|read valid
242 HOLD : in slbit; -- R|read hold
243 SIZEW : out slv(AWIDTH-1 downto 0); -- W|number slots to write
244 SIZER : out slv(AWIDTH-1 downto 0) -- R|number slots to read
245 );
246end component;
247
248component fifo_2c_dram2 is -- fifo, 2 clock, dram based (v2)
249 generic (
250 AWIDTH : positive := 4; -- address width (sets size)
251 DWIDTH : positive := 16); -- data width
252 port (
253 CLKW : in slbit; -- clock (write side)
254 CLKR : in slbit; -- clock (read side)
255 RESETW : in slbit; -- W|reset from write side
256 RESETR : in slbit; -- R|reset from read side
257 DI : in slv(DWIDTH-1 downto 0); -- W|input data
258 ENA : in slbit; -- W|write enable
259 BUSY : out slbit; -- W|write port hold
260 DO : out slv(DWIDTH-1 downto 0); -- R|output data
261 VAL : out slbit; -- R|read valid
262 HOLD : in slbit; -- R|read hold
263 SIZEW : out slv(AWIDTH-1 downto 0); -- W|number slots to write
264 SIZER : out slv(AWIDTH-1 downto 0) -- R|number slots to read
265 );
266end component;
267
268end package memlib;
out DO slv( DWIDTH- 1 downto 0)
AWIDTH positive := 4
in DI slv( DWIDTH- 1 downto 0)
out SIZE slv( AWIDTH- 1 downto 0)
DWIDTH positive := 16
in RESET slbit
in ENA slbit
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)
out BUSY slbit
in HOLD slbit
in CLK slbit
AWIDTH positive := 7
out SIZE slv( AWIDTH downto 0)
DWIDTH positive := 16
in ENA slbit
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)
out BUSY slbit
in HOLD slbit
in CLKW slbit
AWIDTH positive := 5
in CLKR slbit
out SIZER slv( AWIDTH- 1 downto 0)
in RESETR slbit
out SIZEW slv( AWIDTH- 1 downto 0)
DWIDTH positive := 16
in RESETW slbit
in ENA slbit
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)
out BUSY slbit
in HOLD slbit
in CLKW slbit
AWIDTH positive := 5
in CLKR slbit
out SIZER slv( AWIDTH- 1 downto 0)
in RESETR slbit
out SIZEW slv( AWIDTH- 1 downto 0)
DWIDTH positive := 16
in RESETW slbit
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)
AWIDTH positive := 6
out SIZE slv( AWIDTH- 1 downto 0)
DWIDTH positive := 16
AWIDTH positive := 4
in DI slv( DWIDTH- 1 downto 0)
in ADDRB slv( AWIDTH- 1 downto 0)
in ADDRA slv( AWIDTH- 1 downto 0)
out DOB slv( DWIDTH- 1 downto 0)
out DOA slv( DWIDTH- 1 downto 0)
DWIDTH positive := 16
in ADDR slv( AWIDTH- 1 downto 0)
out DO slv( DWIDTH- 1 downto 0)
AWIDTH positive := 4
in DI slv( DWIDTH- 1 downto 0)
in CLK slbit
in WE slbit
DWIDTH positive := 16
in ADDR slv( AWIDTH- 1 downto 0)
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)
in ADDR slv( AWIDTH- 1 downto 0)
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)
in DIA slv( DWIDTH- 1 downto 0)
in ADDRB slv( AWIDTH- 1 downto 0)
in ADDRA slv( AWIDTH- 1 downto 0)
out DOB slv( DWIDTH- 1 downto 0)
in DIB slv( DWIDTH- 1 downto 0)
out DOA slv( DWIDTH- 1 downto 0)
in DIA slv( DWIDTH- 1 downto 0)
in ADDRB slv( AWIDTH- 1 downto 0)
in ADDRA slv( AWIDTH- 1 downto 0)
out DOB slv( DWIDTH- 1 downto 0)
in DIB slv( DWIDTH- 1 downto 0)
out DOA slv( DWIDTH- 1 downto 0)
in DIA slv( DWIDTH- 1 downto 0)
in ADDRB slv( AWIDTH- 1 downto 0)
in ADDRA slv( AWIDTH- 1 downto 0)
out DOB slv( DWIDTH- 1 downto 0)
in DIB slv( DWIDTH- 1 downto 0)
out DOA slv( DWIDTH- 1 downto 0)
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector slv
Definition: slvtypes.vhd:31